Physical Design STA CAD Engineer
Join the Networking Silicon engineering team to develop physical-design and signoff methodologies for high-speed communication SoCs. The role focuses on creating and maintaining STA, backend CAD, power integrity and timing-closure flows used across block and full-chip verification.
You will collaborate with block owners and chip-level teams to drive timing convergence, power/noise analysis, IR-drop/EM checks and back-end verification, and deliver automation and tool-based solutions for multiple projects.
Entry-level / Early Career β typically 2+ years of relevant full-time experience in physical design, STA or backend CAD domains.
The core responsibilities are building and maintaining flows and methodologies to achieve timing and power signoff for networking chips.
Must-have technical skills and professional traits for successful candidates.
B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering preferred; equivalent practical experience is acceptable.
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
