Physical Design - Sr Staff Engineer

Job Title

Physical Design - Sr Staff Engineer

Role Summary

Lead physical implementation for PPA-critical subsystems on advanced process nodes. Work covers floorplanning, place-and-route, clock tree synthesis, power distribution, timing closure and physical verification to deliver tapeout-quality blocks.

The role partners closely with RTL design, DFT and CAD/PNR teams, provides technical leadership for a small engineering team, and drives PPA trade-offs and timing convergence for high-frequency datapaths.

Experience Level

Senior. The posting indicates a senior-level hire with substantial hands-on physical-design experience; the role typically expects 12+ years in physical design or equivalent senior experience (the posting also lists alternative degree+experience thresholds tied to advanced degrees).

Responsibilities

Deliver and lead block-level physical implementation activities and resolve cross-team integration issues.

• Perform floorplanning, place-and-route, clock-tree synthesis, PDN design, timing closure and power optimization for complex SoC blocks.
• Drive timing convergence for high-frequency, datapath-intensive cores using advanced STA methodologies.
• Execute physical verification (DRC/LVS) and formal verification flows; ensure signoff-quality results.
• Make PPA trade-off decisions and tune implementations to meet performance, power and area targets.
• Collaborate with RTL design, DFT and PNR/CAD teams to validate constraints, resolve verification issues and integrate flows.
• Develop and maintain automation scripts and tools; mentor and lead a small team to meet project milestones.

Requirements

Must-have technical skills and experience for immediate contribution.

• Extensive, hands-on physical implementation experience on PPA-critical cores and leading block-level PnR.
• Proven expertise in timing closure and STA for high-frequency datapaths.
• Practical experience with Synopsys ICC2 or Cadence Innovus and signoff STA tools (Tempus/PTSI) or equivalent flows.
• Strong knowledge of PDN design, CTS/clocking architecture and power-optimization techniques.
• Proficiency in scripting and automation (Tcl, Perl) and working in Linux/Unix shell; familiarity with C.
• Experience working in multi-disciplinary teams and resolving issues across design, DFT and PNR flows; strong problem-solving and communication skills.
• Ability to lead and mentor engineers to deliver technical milestones.

Education Requirements

Bachelor's, Master’s or PhD in Computer Science, Electrical/Electronics Engineering or a related engineering/technical field are referenced. The posting gives degree+experience alternatives (Bachelor's +6 years; Master’s +5 years; PhD +4 years) and elsewhere cites 12+ years of physical-design/implementation experience as a typical expectation. Equivalent practical experience at the senior level is considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.