Physical Design Principal Engineer / Director, Custom Silicon Group

Job Title

Physical Design Principal Engineer / Director, Custom Silicon Group

Role Summary

Lead the physical design and signoff effort for next-generation SoCs within the Custom Silicon Group. Own PnR implementation, timing signoff, power analysis, and cross-functional integration from architecture through tapeout.

This role manages and mentors engineering teams, coordinates across multiple sites, and engages with customers and stakeholders to deliver production-ready silicon.

Experience Level

Senior - Principal / Director level. The posting lists multiple experience thresholds (examples in Education Requirements) and also cites senior hiring ranges including 17–25 years of hardware/VLSI/physical design experience.

Responsibilities

Core responsibilities include technical leadership, project ownership, and customer engagement.

• Lead and manage multi-site, cross-functional physical design teams.
• Own PnR implementation: floorplanning, placement, CTS, routing, and post-route activities.
• Ensure timing closure and signoff quality across STA, power analysis, and functional verification domains.
• Resolve cross-team issues involving constraints validation, verification, firmware/software, and validation teams.
• Provide technical leadership in design reviews and executive-level customer engagements.
• Support pre-sales and business development by evaluating feasibility and providing technical estimates.
• Drive resolution of customer-reported silicon issues through coordinated debug and follow-up.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Proven hands-on expertise with PnR flows, floorplanning, placement, CTS, and post-route processes.
• Signoff domain experience: static timing analysis (STA), power analysis, formal and signoff verification, and PDN/IR considerations.
• Experience with low-power and high-performance optimization, and deep sub-micron design challenges (leakage, signal integrity, DFM).
• Track record of delivering tapeouts in advanced process nodes and driving design convergence to meet timing, power, and area targets.
• Ability to coordinate cross-functional teams and communicate technical trade-offs to engineering and customer stakeholders.
• Experience executing responsibilities across multiple sites and mentoring engineering staff.
• Nice-to-have: prior involvement with leading-edge nodes (2nm–5nm), familiarity with LEC/CLP/PDN signoff practices, and pre-sales engineering experience.

Education Requirements

Bachelor's, Master’s, or PhD in Computer Science, Electrical/Electronics Engineering, or a related engineering field are stated in the posting. The listing presents multiple alternative experience thresholds tied to degree level (e.g., Bachelor's +8+ years, Master's +7+ years, PhD +6+ years) and elsewhere cites senior-level ranges such as 17–25 years or 18+ years of physical design/timing signoff experience. Equivalent relevant hardware/VLSI experience is referenced as an alternative to specific degree-year combinations.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.