Physical Design PnR Tile Lead

Job Title

Physical Design PnR Tile Lead

Role Summary

Lead physical implementation for complex SoC tiles at advanced process nodes, driving strategy, execution, and quality across multiple programs and cross-functional teams.

This role partners with Architecture, RTL Design, Timing, CAD, Methodology, Physical Verification, and Full Chip teams. Position located in Markham, ON, Canada.

Experience Level

Senior-level. The posting does not specify explicit years of experience.

Responsibilities

Primary responsibilities include technical leadership, program execution, mentorship, and driving tool/methodology improvements.

• Lead Tile PnR implementation from floorplan through tapeout: placement, CTS, routing, timing closure, congestion management, IR/EM closure, and signoff readiness.
• Define and enforce implementation methodologies and best practices to improve PPA, scalability, and design quality.
• Plan execution, milestones, risk management, and quality metrics for critical IPs and SoC tiles.
• Coordinate cross-functional activities with Design, Timing, CAD, Methodology, Full Chip Floorplan, Power, and Verification teams.
• Drive closure on schedule-critical and tapeout-critical issues and provide regular status to technical and management leadership.
• Mentor Tile PnR engineers, conduct technical reviews, and lead training and knowledge-sharing initiatives.
• Promote adoption of automation and AI-enabled implementation techniques and partner with CAD to improve productivity and predictability.

Requirements

Must-have technical and leadership qualifications are listed below; preferred items are indicated.

• Must-have: Industry experience in physical design with demonstrated technical leadership across multiple projects or product families.
• Must-have: Track record of multiple successful tape-outs at advanced technology nodes.
• Must-have: Proven experience leading critical tiles or IPs and resolving complex implementation challenges.
• Must-have: Deep expertise in congestion analysis, timing architecture, power optimization, and improving PPA.
• Must-have: Experience coordinating work across globally distributed engineering teams and cross-functional stakeholders.
• Preferred / Nice-to-have: Experience with AI-assisted implementation methodologies and automation.
• Preferred / Nice-to-have: Familiarity with ICC2, Fusion Compiler, PrimeTime, RedHawk/Totem, Calibre, and related implementation flows.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or a related field (Bachelor's or Master's degree). No certifications or explicit "equivalent experience" language stated in the posting.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.