Intel Corporation logo

Physical Design Methodology Engineer

Intel Corporation
June 12, 2026
Full-time
Remote friendly (Hillsboro, Oregon, United States)
Worldwide
$164,470 - $269,100 USD yearly
Physical Design Jobs, Level - Mid-Career

Job Title

Physical Design Methodology Engineer

Role Summary

Join the Advanced Design and Foundational IP (ADFIP) team within Design Technology Platform to develop physical-design methodologies, models, and flows for advanced process nodes. The role supports IP and SoC design enablement, silicon validation, and process-design co-optimization to improve power, performance, and area (PPA) for internal and external products.

Experience Level

Mid-level β€” typically 2–6+ years of relevant industry experience depending on advanced degree (see Education Requirements for degree-to-experience guidance).

Responsibilities

You will develop and validate physical-design methodologies and collaborate with design teams to ensure manufacturable, high-performance IP and SoC designs.

  • Create and maintain methodologies, models, and flows for advanced design rules and process nodes.
  • Characterize and validate models via silicon experiments and prototype analysis.
  • Perform Netlist/RTL-to-GDS place-and-route (APR) and signoff tasks to verify design closure.
  • Identify and resolve design vs. process issues; determine root cause and corrective actions.
  • Analyze device and circuit performance across operating conditions to optimize PPA.
  • Drive continuous improvements in design rules, materials, and methodologies to improve yield, quality, and reliability.
  • Communicate process-development results and requirements to IP and SoC teams; support technology enablement and handoff.

Requirements

Must-have technical skills and experience; preferred items listed afterward.

  • Minimum 3+ years experience with digital design and signoff flows.
  • Hands-on experience completing Netlist/RTL-to-GDS place-and-route (APR) and signoff independently.
  • Experience with silicon validation, prototype debugging, and PPA optimization.
  • Familiarity with EDA tools and flows from Cadence and Synopsys.
  • Ability to work independently in a fast-paced environment and collaborate with IP/SoC teams.
  • Preferred: knowledge of semiconductor process technology and Intel process design rules; experience optimizing PPA for low-power GPU/AI designs.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science plus 6+ years industry experience; or Master's degree in those fields plus 4+ years industry experience; or PhD in those fields plus 2+ years industry experience.


About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.

Intel Corporation logo

Date Posted: 2026-06-11