Physical Design Manager

Job Title

Physical Design Manager

Role Summary

Lead the physical design team responsible for end-to-end netlist-to-GDSII implementation, timing signoff, and tapeout. Drive physical feasibility by working closely with RTL, architecture, and DFT teams and optimize power, performance, and area (PPA) across the backend flow.

Experience Level

Senior - requires at least 7 years of relevant experience and proven leadership in backend physical design and tapeout delivery.

Responsibilities

Primary responsibilities include team leadership, project planning, and ownership of the full physical implementation flow:

• Lead and grow the Physical Design team; provide hiring, mentorship, and performance feedback.
• Create work estimates and schedules to meet aggressive tapeout timelines.
• Specify and support procurement and negotiation of EDA tools and licenses.
• Drive floorplanning, macro placement, pin assignment, power grid design, and place-and-route strategies.
• Own static timing analysis (STA), timing constraints, clock tree synthesis (CTS), and timing closure across modes and corners.
• Optimize PPA and address IR/EM, crosstalk, and signal-integrity issues.
• Execute physical signoff checks (DRC, LVS, ERC, antenna fixes) and manage foundry handoff.
• Manage tapeout checklists, final stream-out, and support post-silicon physical debug and bring-up.

Requirements

Must-have qualifications:

• At least 7 years of managerial/backend physical-design experience with leadership responsibility.
• Led 3+ successful tapeouts from netlist to signoff, preferably at advanced technology nodes.
• Hands-on experience with industry-standard EDA tools (examples: Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, Calibre) across floorplanning, P&R, CTS, STA, and signoff.
• Strong backend-debugging skills: STA timing-bottleneck analysis, IR/EM, crosstalk, and DRC/LVS troubleshooting.
• Proven ability to collaborate effectively with RTL, architecture, and DFT teams to influence early physical feasibility.

Nice-to-have:

• Experience at AI or high-performance compute (HPC) chip startups with tight iteration cycles.
• Experience with custom memory/macro floorplanning, hierarchical top-level implementation, or advanced packaging (chiplets, 2.5D/3D integration).
• Hands-on experience developing or maintaining TCL/Python automation for physical design flows.

Education Requirements

Not specified.

About the Company

Company: Normal Computing

Headquarters: New York, NY, USA

Normal Computing develops software and hardware solutions for the semiconductor and AI infrastructure industries, specializing in ASICs for image and video diffusion inference and AI accelerators. The company focuses on architecture and microarchitecture of compute blocks, PE array design, ISA co-design, and FPGA prototyping.