Senior Engineer II - Backend Implementation

Job Title

Senior Engineer II - Backend Implementation

Role Summary

The Backend Implementation engineer performs static timing analysis (STA), timing closure, and low-power checks for large SoC blocks and full-chip designs. The role focuses on developing timing constraints (SDC), closing timing for blocks and top-level, and supporting placement/CTS and power optimization.

Works on advanced process nodes with the implementation team to resolve timing and physical design issues and drive designs toward first-pass silicon success.

Experience Level

Senior-level. Posting specifies 7+ years of Synthesis & STA experience.

Responsibilities

Primary responsibilities include:

• Perform synthesis and STA timing closure (pre- and post-layout) for hierarchical multi-million-gate designs using tools such as Tempus or PrimeTime.
• Generate and maintain timing constraints (SDC) and timing models; run crosstalk and low-power checks.
• Lead and mentor team members; drive implementation activities for complex blocks, subsystems, and full-chip flows.
• Perform CLP and LEC checks at block and full-chip levels; insert DFT logic for block and top level.
• Analyze and debug timing and physical timing challenges; provide guidance for placement and clock tree synthesis (CTS).
• Optimize design performance through timing closure and power optimization techniques.
• Communicate status and issues to project management and cross-functional teams; use metric-driven techniques to improve first-pass silicon outcomes.
• Occasional travel (0%–25%).

Requirements

Must-have and preferred skills:

• Must-have: 7+ years of hands-on Synthesis & STA experience on large hierarchical designs; strong understanding of timing closure and crosstalk analysis.
• Must-have: Expertise with synthesis and STA tools such as Genus, Fusion Compiler, PrimeTime or Tempus.
• Must-have: Knowledge of DFT insertion and good understanding of Verilog.
• Must-have: Strong scripting skills (Perl, Tcl, Shell, and/or Python) and effective written and verbal communication.
• Nice-to-have: Experience with Conformal LEC and CLP, UPF/CPF, and working on advanced process nodes (16nm down to 3nm).

Education Requirements

At least a B.E. / B.Tech or an M.Tech degree in Electronics (electrical/electronics or closely related technical field) as specified in the posting.

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.