Physical Design Manager

Job Title

Physical Design Manager

Role Summary

Lead a physical design engineering team responsible for delivering production-quality physical implementation and tapeout for advanced ASIC/SoC projects. The role combines technical leadership, cross-functional execution, and ownership of predictable, high-quality tapeout results.

Experience Level

Senior - typically 12+ years of experience in ASIC or SoC physical design with significant experience leading teams or major project areas.

Responsibilities

Primary responsibilities include technical leadership, program execution, and continuous improvement of physical design flow and team capabilities.

• Lead, mentor, and grow a team of physical design engineers in Bengaluru.
• Own physical implementation planning and execution from netlist through signoff and tapeout.
• Drive floorplanning, power planning, placement, clock-tree synthesis, routing, optimization, extraction, timing closure, physical verification, and signoff.
• Establish technical direction, project priorities, execution plans, and quality standards for the team.
• Partner with RTL design, microarchitecture, DFT, STA, CAD, verification, packaging, and product engineering teams.
• Identify physical design risks early and lead mitigation across schedule, power, performance, area, and manufacturability.
• Review and improve design methodologies, automation, flows, tools, and engineering practices.
• Ensure effective use of metrics, reviews, documentation, and lessons learned to improve predictability and execution quality.
• Contribute to staffing plans, capability development, performance management, and succession planning.
• Communicate technical status, trade-offs, risks, and recommendations clearly to engineering leadership.

Requirements

Must-have technical experience and leadership skills required to execute complex physical design projects.

• 12+ years of ASIC or SoC physical design experience with significant experience leading teams or major project areas.
• Hands-on understanding of the complete physical design flow from synthesis handoff through signoff.
• Practical experience with floorplanning, power distribution, placement, CTS, routing, timing closure, signal integrity, IR drop, electromigration, physical verification, and DFM considerations.
• Demonstrated track record delivering complex designs to tapeout in advanced process technologies.
• Strong knowledge of timing constraints, multi-voltage or low-power design, ECO implementation, and signoff methodologies.
• Experience collaborating across geographically distributed, cross-functional engineering teams.
• Strong problem-solving, planning, prioritization, communication, and people-leadership skills.

Nice-to-have:

• Experience with high-performance, high-volume networking, compute, FPGA, or other complex SoC designs.
• Familiarity with industry-standard implementation and signoff tools from leading EDA vendors.
• Experience developing automation using Tcl, Python, Perl, or similar scripting languages.
• Experience defining physical design methodologies, flows, dashboards, and productivity improvements.
• Knowledge of advanced-node challenges such as congestion, variability, multicorner-multimode closure, and restrictive design rules.

Education Requirements

Bachelor's or master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.