Physical Design Lead/Manager

Job Title

Physical Design Lead/Manager

Role Summary

Lead physical implementation and tape-out of high-speed mixed-signal SoCs (high-speed ADC/DAC and interfaces). Define implementation methodology, coordinate with architecture, front-end and CAD teams, and ensure production-quality physical designs.

Manage and mentor the physical design and custom layout teams and liaise with foundry for technology, schedule, and signoff.

Experience Level

Senior-level. Requires 8+ years of SoC physical design experience and 3+ years of project/team leadership.

Responsibilities

Primary responsibilities include end-to-end physical implementation, toolflow setup, verification and team leadership:

• Own and drive physical implementation of mixed-signal SoCs with high-speed ADC/DAC and interfaces (PCIe, LPDDR, MIPI, USB2/3, Gigabit Ethernet).
• Define physical implementation methodologies and develop UPF power intent and methodology.
• Perform floorplanning, power planning, clock grid design and top-level integration.
• Implement and verify designs at block and full-chip levels; generate SDF files.
• Execute placement, timing closure, routing, extraction, and physical verification (DRC & LVS); run SI, crosstalk, EM/IR and DFM checks.
• Set up EDA tools, develop automation scripts, and maintain RTL-to-GDSII flows.
• Lead tape-out activities and coordinate with foundry on technology, schedule and signoff.
• Manage, mentor and review work from PD and custom layout engineers; update custom layout as required and release GDSII to fabs.

Requirements

Must-have and preferred technical qualifications:

• 8+ years of physical design experience in SoCs.
• 3+ years of experience managing projects and leading teams.
• Hands-on expertise in floorplanning, power planning, UPF methodology, logic and clock-tree synthesis, placement, timing closure, routing, extraction, and physical verification (DRC & LVS).
• Experience with crosstalk analysis, EM/IR and signal/power integrity checks.
• Full-chip/top-level expertise with multiple tape-outs.
• Experience with SCAN, BIST and ATPG.
• Strong scripting skills in TCL, Perl and Python.
• Required: experience with sub-40 nm process nodes.
• Desirable: experience with double patterning; familiarity with Cadence or Synopsys RTL-to-GDSII flows.
• Experience interacting with foundry on technology, schedule and signoff.

Education Requirements

Bachelor of Science in Electrical Engineering (BSEE) required; Master of Science in Electrical Engineering (MSEE) preferred. No certifications or equivalent-experience language specified in the posting.

About the Company

Company: Omni Design Technologies

Headquarters: Hyderabad, India

Omni Design Technologies specializes in the development of advanced solutions for electronic design automation, focusing on ASIC and FPGA verification processes. The company provides high-quality verification tools and resources for engineers in the semiconductor industry, ensuring efficient design and reliable performance.