Physical Design Lead (High-Speed IPs)

Job Title

Physical Design Lead (High-Speed IPs)

Role Summary

Lead physical implementation for high-speed interface IPs (DDR/LPDDR/GDDR, PCIe, SerDes and mixed-signal PHYs) as part of the CT Physical Design team. Drive end-to-end implementation, signoff, and tapeout coordination with architects, circuit designers, RTL, SI/PI, package, and SoC teams.

Experience Level

Senior-level (Member of Technical Staff / Lead). Preferred 10+ years of industry experience in physical design and multiple successful tape-outs on advanced nodes.

Responsibilities

Accountable for technical leadership and delivery of complex high-speed IPs through implementation and signoff.

• Lead physical implementation activities: floorplanning, power planning, placement, clock architecture, CTS, timing closure, and physical verification.
• Drive timing closure for high-frequency datapaths and complex clock/distribution networks.
• Collaborate with architects, circuit designers, RTL, AMS, SI/PI, package, product engineering, SoC, CAD, and EDA vendors to meet PPA and schedule targets.
• Own tapeout signoff and coordinate cross-functional signoff requirements.
• Develop and deploy implementation methodologies, automation, and AI-assisted flows to improve quality and productivity.
• Mentor and grow junior engineers; provide technical leadership across IP programs and geographies.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Extensive hands-on physical design and signoff experience, including STA and timing closure for high-speed designs.
• Proven experience with clock architecture, CTS, floorplanning, power planning, and physical verification signoff.
• Practical SI/PI analysis experience and familiarity with IR/EM considerations for IPs.
• Experience with industry-standard implementation and signoff EDA flows (Cadence, Synopsys, or equivalent).
• Strong scripting skills (Tcl, Python) for automation and methodology development.
• Demonstrated ability to lead cross-functional teams, mentor engineers, and drive technical initiatives.
• Experience improving flows via automation or AI-assisted techniques.
• Excellent communication and collaboration skills across distributed teams.

Nice-to-have:

• Experience delivering multiple tape-outs on advanced nodes (N3/N4/N5 or equivalent).
• Experience with low-power design methodologies (UPF/CPF) and advanced node design practices.
• Familiarity with AI-assisted design flows and EDA vendor collaborations.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, VLSI Design, or a related technical field (as stated in the posting).

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.