Physical Design Lead

Job Title

Physical Design Lead

Role Summary

Lead end-to-end physical implementation of complex SoCs and IPs on advanced technology nodes, owning large design partitions or top‑level physical design activities to meet power, performance, area (PPA), quality and schedule goals.

Provide technical leadership, mentor engineers, improve implementation methodologies and coordinate with architecture, RTL, verification, package and technology teams to achieve production-quality signoff.

Experience Level

Senior - typically requires 15+ years of ASIC/SoC physical design experience.

Responsibilities

Accountable for physical implementation, closure and signoff of complex SoC/IP designs and for improving implementation flows and team capabilities.

• Lead RTL-to-GDSII implementation: synthesis, floorplanning, power planning, place-and-route, CTS, timing closure, physical verification and tapeout.
• Own block-, subsystem- or top-level physical implementations and drive to production signoff.
• Perform advanced static timing analysis (STA), MCMM optimization, timing ECOs and signoff closure.
• Manage power, performance, area, signal integrity, electromigration, IR-drop, reliability and manufacturability targets.
• Develop and optimize physical design methodologies, automation frameworks, flows and scripts.
• Analyze critical timing paths, congestion, routing and power bottlenecks and implement solutions to meet PPA goals.
• Drive DRC, LVS, antenna checks, density and metal-fill verification and tapeout readiness reviews.
• Evaluate and deploy EDA tools and advanced implementation techniques.
• Mentor and guide engineers; lead cross-functional implementation efforts and deliver implementation reports and signoff documentation.

Requirements

Must-have technical experience and skills required for immediate contribution. Education requirements are listed separately below.

• 15+ years hands-on ASIC/SoC physical design experience with successful tapeouts on advanced process technologies.
• Extensive hands-on experience in synthesis, floorplanning, place-and-route, timing analysis, physical verification and signoff closure.
• Deep understanding of MCMM timing closure methodologies, timing constraint development and ECO implementation.
• Hands-on experience with industry-standard EDA tools such as Cadence Innovus and Tempus; Synopsys Fusion Compiler, ICC2 and PrimeTime; and EM/IR tools like Ansys RedHawk or equivalents.
• Experience with signal integrity analysis, crosstalk mitigation, electromigration and IR-drop closure; strong DFM awareness.
• Proficiency in Tcl scripting and working knowledge of Python and/or Perl for automation and flow development.
• Experience with advanced process nodes (16nm FinFET and below); experience at 7nm/5nm is preferred.
• Proven ability to drive complex multi-million gate SoC implementations and meet aggressive PPA targets.
• Strong problem-solving, analytical, debugging, communication and stakeholder-management skills.

Nice-to-have:

• Experience leading physical implementation and signoff across multiple sites and developing organization-wide methodologies and automation frameworks.
• Familiarity with variation-aware timing closure, congestion management and AI-assisted design optimization techniques.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science or a related technical field.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.