Physical Design / Implementation Lead

Job Title

Physical Design / Implementation Lead

Role Summary

Lead the physical design and implementation function for SoCs, defining and operating the RTL-to-tapeout flow on advanced process nodes. The role owns synthesis, P&R, timing closure, power/clock distribution, physical verification, and IP/library management across multi-site teams.

This is a hands-on leadership position responsible for building and managing a physical design team and coordinating cross-functional integration with RTL, DV, analog/mixed-signal, and system teams. Position is full-time onsite in Austin, TX or Sunnyvale/San Jose, CA.

Experience Level

Senior-level — lead/manager role requiring substantial senior back-end SoC implementation and tapeout leadership experience.

Responsibilities

Own and deliver SoC and subsystem implementations end-to-end; build the team and processes required to tape out complex chips on leading-edge nodes.

• Lead RTL-to-tapeout implementation: synthesis, floorplan, P&R, timing closure, ECOs, and finalization for GDSII delivery.
• Optimize and automate synthesis and timing-closure flows across blocks and subsystems.
• Define and optimize power and clock distribution architectures at chip scale.
• Integrate analog/mixed-signal blocks into the digital implementation flow and manage cross-team processes.
• Own physical verification, signoff flows, and IP/library management for the digital org.
• Manage hiring, ramping, and performance of a multi-site physical design team.
• Drive intake and qualification of new process technologies and toolchain updates.
• Collaborate with RTL, DV, analog, and system leads on schedules and implementation tradeoffs.

Requirements

Must-have experience and skills required to perform the role; preferred items listed separately.

• Must-have: Proven track record leading physical design/implementation on large, complex SoCs through tapeout or equivalent broad ownership of synthesis, timing closure, power, and physical verification.
• Must-have: Hands-on advanced-node implementation experience; FinFET-class node experience (7nm–3nm) required; TSMC N3 strongly preferred.
• Must-have: Deep experience in power and clock architecture and delivery at chip scale (CPU-class or very large SoC experience preferred).
• Must-have: Experience building, hiring, and growing a physical design team and driving engineering execution.
• Must-have: Practical ownership of physical verification and IP/library flows.
• Nice-to-have: Experience integrating analog/mixed-signal blocks into digital implementation flows.
• Nice-to-have: Familiarity with Cadence toolchain and common EDA automation practices.

Education Requirements

Not specified.

About the Company

Company: Neurophos

Headquarters: Sunnyvale, California, United States

Startup developing silicon-photonic AI accelerator chips that use programmable metasurfaces and dense optical cells to perform matrix multiplications at the speed of light, targeting large-scale AI inference with much higher energy efficiency and performance than traditional electronic approaches.