Physical Design Implementation and STA Lead

Job Title

Physical Design Implementation and STA Lead

Role Summary

The Physical Design Implementation and STA Lead is an individual contributor with project leadership responsibility who drives block- and SoC-level physical implementation and static timing analysis (STA) from floorplanning through final timing closure. This role partners with RTL, architecture, DFT, CAD, library, packaging, and signoff teams to deliver timing- and PPA-compliant designs for advanced FPGA SoCs.

Bay Area salary range: $149,100 - $215,000 USD.

Experience Level

Senior-level. The posting specifies 7+ years of industry experience in physical design, physical implementation, or static timing analysis.

Responsibilities

Primary responsibilities include:

• Lead block-level physical implementation: synthesis, floorplanning, place-and-route, clock tree synthesis (CTS), optimization, and ECO closure.
• Support SoC-level implementation: floorplanning, partitioning, and integration strategies for top-level timing and PPA goals.
• Develop and maintain implementation constraints (SDC) and power intent (UPF) to meet timing, power, and area requirements.
• Lead static timing analysis (STA) and timing closure across multi-mode multi-corner (MMMC) scenarios using PrimeTime or equivalent tools.
• Identify and resolve setup, hold, recovery/removal, SI/crosstalk, and clock-related timing issues and drive timing-driven ECOs with RTL and physical teams.
• Execute signoff and physical verification activities (IR drop, EM, DRC, LVS, antenna checks) and analyze congestion, routing, and clock quality.
• Develop automation (Tcl, Python) and evaluate ML/AI-assisted implementation techniques to improve closure efficiency.
• Provide technical leadership, mentor junior engineers, and contribute reusable methodologies and best practices.

Requirements

Must-have and preferred technical requirements:

• Must-have: 7+ years of industry experience in physical design, physical implementation, or SoC backend development.
• Must-have: 5+ years performing block-level implementation (synthesis, floorplan, P&R, CTS, optimization, ECO).
• Must-have: 3+ years performing static timing analysis with Synopsys PrimeTime or equivalent, including MMMC analysis.
• Must-have: Practical experience creating and validating constraints (SDC, UPF) and driving timing closure activities.
• Must-have: Experience with signoff-quality analysis: IR drop, EM, DRC/LVS awareness, routing/congestion analysis, and PPA tradeoffs.
• Nice-to-have: 10+ years of experience in physical design and STA for advanced semiconductor products.
• Nice-to-have: Experience with advanced process nodes (7nm, 5nm, or below) and SoC-level top-level timing closure.
• Nice-to-have: Experience with high-speed interfaces (PCIe, Ethernet, SerDes, DDR/LPDDR, HBM) and related signal integrity considerations.
• Nice-to-have: Familiarity with ML/AI-assisted implementation flows and experience developing automation and CAD integrations.

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline (specified in minimum qualifications). Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline is listed as preferred.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.