Physical Design Flow & Methodology Engineer

Job Title

Physical Design Flow & Methodology Engineer

Role Summary

Lead physical-design flow development and PPA optimization for a soft IP (processor) delivered as RTL and implementation collateral. Work with architecture, RTL, and delivery teams to build portable RTL-to-GDS reference flows and provide hands-on support to SoC integrators through tapeout.

Role includes internal flow development, benchmarking EDA changes, and acting as the primary physical-design contact for customer integrations and tapeout support.

Experience Level

Senior level — requires 7+ years of ASIC or processor IP physical-design experience focused on PPA optimization and flow development across advanced nodes.

Responsibilities

Primary responsibilities cover PPA analysis, reference flow development, and customer tapeout support.

• Drive timing, area, leakage, and dynamic-power analysis and optimizations across IP configurations and process nodes.
• Apply low-power techniques and synthesis/place-and-route knobs to meet frequency and area targets.
• Characterize design-space tradeoffs and build PPA models for customer evaluations and pre-sales support.
• Develop and maintain a portable RTL-to-GDS reference flow with BKMs, SDC templates, floorplan scripts, and integration guidelines.
• Implement automation (TCL, Python) to accelerate flow development and improve repeatability; leverage AI coding tools where effective.
• Qualify EDA tool updates, benchmark QoR impact, and incorporate validated changes into the reference flow.
• Serve as primary PD contact for customers, adapt the reference flow to foundry PDKs and customer environments, and troubleshoot timing/congestion/power/flow failures.
• Support FAE and BD teams with PPA feasibility studies and integration guidance through tapeout.
• Document methodologies, maintain node bring-up guidelines, and communicate learnings to architecture and RTL teams.

Requirements

Must-have technical skills and experience for the role.

• 7+ years of ASIC or processor IP physical-design experience focused on PPA optimization and flow development across advanced nodes.
• Proficiency with industry-standard physical-design tools (Synopsys or Cadence) for synthesis, place-and-route, and timing analysis.
• Experience with advanced FinFET process nodes (16nm and below); multi-node experience preferred.
• Strong TCL scripting and Python automation skills; experience using AI tools to accelerate script development is a plus.
• Deep understanding of synthesis and P&R levers affecting timing, cell selection, congestion, and power intent; hands-on MCMM timing analysis experience.
• Hands-on experience with low-power design techniques (clock gating, multi-Vt, operand isolation) and their physical implications.
• Understanding of DFT concepts (scan, ICG bypass) and their impact on physical design.

Nice-to-have

• Experience delivering soft IP to external customers and supporting SoC integrators through tapeout.
• Background in AI accelerator, NPU, or DSP processor IP implementation.
• Exposure to metrics-driven QoR tracking and large-scale synthesis run management.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field (BS/MS in EE, CE, or similar) was requested in the source posting.

About the Company

Company: Quadric

Headquarters: Burlingame, California, United States

Quadric is building the world’s first supercomputer designed for the real-time needs of edge devices. Founded in 2016, the company empowers developers across industries with innovative general-purpose neural processing unit (GPNPU) architecture for neural network workloads. Co-founded by technologists from MIT and Carnegie Mellon, Quadric aims to enable groundbreaking technology development.