Physical Design Engineer (Staff)
SynopsysJob Title
Physical Design Engineer (Staff)
Role Summary
Senior physical design engineer responsible for RTL-to-GDS implementation and digital backend delivery for on-chip silicon lifecycle monitors. Owns flows from synthesis through tapeout and collaborates with architecture and circuit teams to deliver timing-closed, production silicon.
Onsite role based in Bengaluru working with cross-functional product teams to drive signoff and tapeout success on advanced process nodes.
Experience Level
Senior-level (Staff). See Education Requirements for formal degree and experience expectation.
Responsibilities
Key responsibilities include implementation, verification, and flow development for digital backend and signoff.
- Design and implement RTL-to-GDS flows for on-chip lifecycle monitors (process, voltage, temperature, glitch, droop sensors).
- Own backend implementation: floorplanning, power planning, multivoltage design with UPF and VCLP, placement, CTS, and routing.
- Develop and close pre-layout and post-layout STA across multiple corners using PrimeTime and PrimeTime PX; create SDC and generate timing ECOs.
- Execute physical verification and signoff: DRC, LVS, PERC, ERC, antenna checks, EMIR, and power signoff using ICV and RedHawk.
- Build and refine design flows and automation in collaboration with architecture and circuit teams; script in TCL and Perl.
- Iterate on timing and DRV ECOs to meet PPA targets on advanced FinFET and GAA nodes.
Requirements
Must-have technical skills and tool experience.
- Proven tapeout success on advanced nodes (14nm–2nm).
- Strong experience with DRC, LVS, DFM cleaning, and generating ECOs for design rule and timing closure.
- Proficiency with Synopsys toolset: Fusion Compiler, VCLP, PrimeTime, PrimeTime PX, ICV, and RedHawk.
- Solid understanding of multivoltage design concepts including UPF, SDC constraints, OCV/POCV, derates, and crosstalk.
- Experience scripting automation in TCL and Perl to customize flows and methodologies.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering. The posting specifies 5+ years of experience in physical design, physical verification, and static timing analysis at IP, block, or full-chip level.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
