Physical Design Engineer, Staff
QualcommJob Title
Physical Design Engineer, Staff
Role Summary
Member of the ASIC physical-design team responsible for end-to-end physical implementation and sign-off of SoC blocks. Work with cross-functional engineering teams to deliver floorplanning, place-and-route, timing closure, power-network validation and sign-off-ready GDS2 deliverables.
Experience Level
Senior (Staff). Typical experience range indicated: 4–10 years in physical design; degree-dependent minimums listed (see Education Requirements).
Responsibilities
Primary responsibilities include ownership of physical design tasks from netlist to GDS2 and ensuring sign-off quality:
- Lead floorplanning, placement, routing and clock-tree synthesis (CTS) for assigned blocks.
- Execute full PD flow to generate sign-off deliverables (netlist→GDS2), including power- and timing-related checks.
- Implement low-power techniques (Voltage Islands, power domain implementation) and verify PDN integrity.
- Debug and resolve congestion, CTS, timing closure, and other implementation issues.
- Run and interpret sign-off checks (PV/PDN/STA/FV/CLP/Scan/DRC) and iterate with EDA flows.
- Develop and maintain automation and scripts to improve flows and productivity.
- Collaborate with global teams and communicate status, issues, and trade-offs to stakeholders.
Requirements
Must-have technical skills and experience for successful performance in this role:
- Thorough knowledge of ASIC place-and-route flow and methodology.
- Hands-on experience executing physical-design ownership from netlist to GDS2, including power/LEC/low-power checks, PDN validation and STA closure.
- Practical experience with Voltage Islands and low-power implementation techniques and flows.
- Strong debugging skills for congestion and CTS-related issues.
- Expertise with P&R tools such as Cadence Innovus / Fusion Compiler and related flows.
- Familiarity with sign-off methodologies and tools (timing, power, functional verification, DRC/scan flows).
- Proficient scripting skills (TCL, Perl, Python) to automate flows and checks.
- Ability to work effectively in global teams and communicate technical status and risks.
Nice-to-have:
- Experience improving and scaling existing methodologies and automation for large SoC designs.
Education Requirements
Bachelor's, Master’s or PhD in Computer Science, Electrical/Electronics Engineering, Engineering or a related field. Minimum experience varies by degree: Bachelor's +4 years, Master's +3 years, PhD +2 years of relevant hardware/physical-design experience. "Related field" and equivalent practical experience are accepted per the posting.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
