Physical Design Engineer - Staff
SynopsysJob Title
Physical Design Engineer - Staff
Role Summary
Senior physical design engineer responsible for RTL-to-GDS backend flow and signoff for on-chip silicon lifecycle monitors and IP. Work spans floorplanning, synthesis, placement, CTS, routing, STA, and physical verification to deliver timing-closed designs on advanced nodes.
Experience Level
Senior — typically 5+ years of experience in physical design, physical verification, and static timing analysis (STA).
Responsibilities
Key responsibilities include owning digital backend implementation, signoff, and flow automation for complex IP and chip blocks.
- Design and implement RTL-to-GDS flows for on-chip monitors (process, voltage, temperature, glitch, droop).
- Own backend from synthesis through tapeout: floorplanning, power planning, multivoltage (UPF/VCLP), placement, CTS, and routing.
- Develop and close pre-layout and post-layout STA across multiple corners using PrimeTime and PrimeTime PX; create SDCs and generate timing ECOs.
- Execute physical verification and signoff: DRC, LVS, PERC, ERC, antenna checks, EMIR, and power signoff using ICV and RedHawk.
- Build and refine design flows with architecture and circuit teams; script automation in TCL and Perl.
- Generate and iterate timing and DRV ECOs to meet PPA targets on advanced FinFET and GAA nodes.
Requirements
Must-have technical skills and domain experience.
- Proven tapeout success on advanced nodes (14nm, 10nm, 7nm, 5nm, 3nm, or 2nm).
- Experience with DRC, LVS, DFM cleaning, and producing ECOs for DRV and timing closure.
- Proficiency with Synopsys tools such as Fusion Compiler, VCLP, PrimeTime, PrimeTime PX, ICV, and RedHawk.
- Strong understanding of multivoltage design, UPF, SDC constraints, OCV/POCV, derates, and crosstalk.
- Experience scripting automation and flow customization using TCL and Perl.
- Ability to debug timing, floorplan, LVS, and power-grid issues across synthesis and post-route stages.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering. The role expects 5+ years of hands-on experience in physical design, physical verification, and STA at IP, block, or full-chip level.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
