Physical Design Engineer - STA

Job Title

Physical Design Engineer - STA

Role Summary

Timing engineer responsible for static timing analysis (STA) and timing closure for high-performance ASIC designs. Work on timing signoff, constraint development, ECO implementation, and collaboration across RTL, DFT, and physical design teams to meet chip performance targets across corners and modes.

Experience Level

Senior — 7+ years industry experience (experience requirement listed by employer).

Responsibilities

Primary duties focus on STA, timing closure, and automation to achieve target performance on complex SoCs.

• Perform static timing analysis and drive timing closure across corners, voltages, and modes.
• Develop, debug, and validate SDC constraints and constraints flows; create and apply ECOs.
• Analyze and mitigate timing issues related to noise, crosstalk, and OCV effects.
• Collaborate with RTL, DFT, and physical design teams to identify and resolve critical paths.
• Implement and maintain automation and scripts to improve timing flow efficiency.
• Support signoff/tapeout activities and produce timing reports and documentation for tapeouts.
• Contribute to timing methodology, tool flow enhancements, and closure strategies for sub-micron processes.

Requirements

Key must-have skills and constraints for candidates. Nice-to-have items are listed separately.

• Must-have: 7+ years of industry experience with a proven record of successful tapeouts.
• Must-have: Deep knowledge of STA tools and techniques, including analysis of noise, crosstalk, and OCV.
• Must-have: Proficiency writing and debugging SDC constraints, creating ECOs, and developing timing closure strategies.
• Must-have: Strong scripting skills (Python, Perl, TCL) for automation and flow development.
• Must-have: Familiarity with SPICE modeling and worst-case corner analysis.
• Ability to work in a hybrid model based out of Austin, TX; Fort Collins, CO; or Santa Clara, CA.
• Must-have: Employment contingent on eligibility to access U.S. export-controlled technology (citizenship/permanent residency or ability to obtain required licenses).
• Nice-to-have: Experience with RISC-V CPU or AI SoC timing, advanced nodes, or prior work integrating DFT and physical design timing flows.

Education Requirements

Not specified.

About the Company

Company: Tenstorrent

Headquarters: Austin, Texas, United States

Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.