Physical Design Engineer, Sr Staff

Job Title

Senior Staff Physical Design Engineer

Role Summary

Lead technical delivery for full-chip and multi-die physical implementation on advanced TSMC FinFET nodes (N5/N4P/N3). Own backend flow architecture, methodology, automation, and tapeout readiness while coordinating with foundry, EDA vendors, and cross-functional teams.

Experience Level

Senior - role expects experienced engineering leadership. Typical candidates have substantial senior-level experience (see Requirements for technical expectations and Education Requirements for formal degree guidance).

Responsibilities

Accountable for physical design strategy, methodology, automation, and mentoring to deliver advanced-node tapeouts.

• Architect and own full-chip physical design strategy: floorplanning, PDN, clock architecture, PnR, and timing closure.
• Define and drive backend methodology standards for advanced-node tapeouts (N5/N4P/N3).
• Lead timing closure: MCMM, OCV, advanced ECO strategies, and cross-corner sign-off.
• Oversee signal integrity, power integrity, EM/IR, and reliability analysis for full-chip designs.
• Design and implement scalable PD flow infrastructure and automation using Python and TCL, including regression and sign-off reporting.
• Champion integration of Agentic AI into PD flows: define use cases, prototype autonomous agents, and evaluate tools.
• Lead cross-functional design reviews and interface with foundry and EDA vendors.
• Mentor and provide technical guidance to junior and mid-level PD engineers.

Requirements

Must-have technical skills and experience for immediate contribution and leadership.

• Proven track record of tapeouts on FinFET nodes (N7 and below) and deep expertise in full-chip and block-level floorplanning, clock architecture, STA, PnR, and physical sign-off.
• Expert proficiency with EDA tools such as Synopsys ICC2/Fusion, Cadence Innovus, Calibre, PrimeTime, RedHawk/Voltus, StarRC/Quantus.
• Advanced Python and TCL scripting; experience architecting large-scale PD automation frameworks and flow infrastructure.
• Experience designing, implementing, and owning end-to-end backend design flows at a team or organization level.
• Demonstrated vision or practical experience applying Agentic AI or LLM-assisted techniques to EDA challenges (automation, optimization, debugging).
• Strong communication skills; able to present methodology decisions, risk assessments, and tapeout readiness to senior management.
• Experience with power optimization techniques (DVFS, multi-Vt, power domains, UPF/CPF) and sign-off criteria.

Nice-to-have:

• Experience with chiplets, 2.5D/3D IC physical design, or advanced packaging.
• Familiarity with AI/ML-driven EDA tool evaluation and vendor collaboration.
• Prior tech lead, staff, or senior leadership roles guiding multi-team delivery.

Education Requirements

Minimum qualifications in the source specify formal degree options with corresponding experience: Bachelor's degree in Science, Engineering, or related field with 6+ years' ASIC design/verification/validation/integration experience; OR Master's degree in Science, Engineering, or related field with 5+ years; OR PhD in Science, Engineering, or related field with 4+ years. Equivalent practical experience will be considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.