Physical Design Engineer, Reality Labs Silicon

Job Title

Physical Design Engineer, Reality Labs Silicon

Role Summary

Translate RTL into optimized silicon implementations for VR/AR systems, focusing on floorplanning, placement, clock tree synthesis, routing, and signoff. Join the Reality Labs Silicon / Silicon Engineering team to collaborate with architects, RTL designers, verification, and DFT teams to meet power, performance, and area targets for wearable and spatial-computing devices.

Experience Level

Mid-level. Typical candidates have approximately 6+ years of hands-on physical design experience for complex digital ASICs or SoCs.

Responsibilities

Deliver physical implementation of complex blocks and subsystems and improve physical design flows and methodologies.

• Lead physical implementation from floorplanning through tapeout, including placement, CTS, routing, and signoff.
• Define and drive physical design methodology, constraints, and flows to meet PPA (power, performance, area) targets.
• Perform static timing analysis and timing closure across multiple process corners and operating conditions.
• Develop and optimize power delivery network strategies; perform IR drop and electromigration analysis and sign-off.
• Collaborate with RTL architects and designers to influence microarchitecture and floorplan decisions.
• Partner with verification and DFT teams to ensure testability and functional correctness of physical implementations.
• Drive physical verification sign-off including DRC, LVS, and antenna checks in advanced nodes.
• Identify and resolve implementation bottlenecks related to congestion, timing, and power through analysis and optimization.
• Contribute to development and automation of internal flows, scripts, and tools to increase team efficiency.

Requirements

Must-have technical experience and skills.

• 6+ years of physical design experience for complex digital ASICs or SoCs, including floorplanning, placement, CTS, routing, and sign-off.
• 6+ years of experience with static timing analysis and timing closure in advanced process nodes (7nm or below).
• Experience with industry-standard physical design EDA tools (for example Cadence Innovus, Synopsys ICC2, or equivalent).
• Experience with physical verification flows including DRC, LVS, and antenna sign-off.
• Experience with power analysis and power delivery network implementation, including IR drop and electromigration analysis.

Nice-to-have / preferred:

• Experience with Synopsys Fusion Compiler (FusionPilot/ConfigAI), StarRC, PrimeTime, or similar advanced implementation tools.
• Experience with low-power mobile/wearable SoCs, multi-voltage domains, and power-gating implementation.
• Experience developing automation scripts using Python or Tcl for physical design flows.
• Familiarity with RTL/physical co-design methodologies and advanced-node design kits (5nm or below).

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.