Physical Design Engineer (PnR)

Job Title

Physical Design Engineer (PnR)

Role Summary

Implement and close high-performance partitions of an AI SoC, owning the implementation flow from synthesis through tapeout. Work in a small cross-functional physical design team alongside architects, RTL designers, and DFT engineers to meet timing, power, and signoff goals.

Hybrid role based out of Austin, TX; Santa Clara, CA; or Fort Collins, CO. The team focuses on Synopsys-based flows for production tapeouts.

Experience Level

Mid-level. The company is open to a range of seniorities and will place candidates at an appropriate level during interviews.

Responsibilities

Primary responsibilities include ownership of assigned partitions through implementation and signoff:

• Execute synthesis, place-and-route (PNR), and static timing analysis (STA) for assigned blocks.
• Drive timing closure, power intent implementation, and EM/IR closure for your partitions.
• Coordinate and drive logical equivalence checking (LEC/Formality) and physical verification signoff (DRC/LVS) in collaboration with methodology owners.
• Integrate SoC interface IP and analog/mixed-signal macros (e.g., PLL/DLL) into the physical design flow as required.
• Collaborate with architects, RTL designers, DFT engineers, and verification teams to resolve implementation issues and meet tapeout milestones.
• Own delivery commitments for your block or subsystem within a small, accountable team.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

• Must-have: Practical experience with synthesis and place-and-route flows, especially Synopsys Design Compiler / Fusion Compiler and IC Compiler II.
• Must-have: Experience performing STA and implementing multi-clock/CDC-aware designs in production flows.
• Must-have: Proven ability to drive signoff activities (LEC/Formality, EM/IR closure, physical verification) in coordination with methodology teams.
• Must-have: Comfortable owning a block or subsystem in a small cross-functional physical design team and meeting tapeout milestones.
• Nice-to-have: Depth in UPF / multi-voltage power domains and power intent validation.
• Nice-to-have: Experience integrating SoC interface IP (e.g. I3C, UART) and analog/mixed-signal macros.
• Nice-to-have: Familiarity with DFT-aware physical implementation (OCC/MBIST) and broader signoff domains (DRC/LVS, EM/IR).
• Important: This position requires access to U.S. export-controlled technology; offers may be contingent on citizenship/permanent-residency status or a prior export license.

Education Requirements

Not specified.

About the Company

Company: Tenstorrent

Headquarters: Austin, Texas, United States

Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.