Physical Design Engineer, PnR

Job Title

Physical Design Engineer, PnR

Role Summary

Implement high-performance partitions for an AI SoC, owning the flow from synthesis through tapeout. Work in a small cross-functional physical design team to meet performance, power, area, and signoff targets.

The role is hybrid and based out of Austin, TX; Santa Clara, CA; or Fort Collins, CO.

Experience Level

Mid-level. The team welcomes candidates at various experience levels; final level and offer will be determined during the interview process.

Responsibilities

Primary day-to-day responsibilities include implementation, signoff, and cross-team coordination for assigned SoC partitions.

• Execute synthesis, place-and-route (PnR), and static timing analysis (STA) for assigned partitions using a Synopsys-based flow.
• Drive timing closure and EM/IR closure for partitions; ensure power intent (UPF) matches implementation and resolve power-related issues.
• Coordinate and drive logical equivalence checking (LEC/Formality), physical verification (DRC/LVS), and signoff activities with methodology owners.
• Integrate analog/mixed-signal macros (PLL/DLL), DFT features (OCC/MBIST), and SoC interface IP into the physical implementation as needed.
• Collaborate with architects, RTL designers, DFT, and verification engineers to resolve implementation and signoff issues.
• Own block/subsystem implementation and meet tapeout milestones with clear communication and accountability.

Requirements

Must-have skills and qualifications are listed first; nice-to-have items follow.

• Must-have: Hands-on experience with synthesis and place-and-route flows, especially Synopsys Design Compiler / Fusion Compiler and IC Compiler II.
• Must-have: Strong experience with STA, timing closure, and signoff coordination (including familiarity with DRC/LVS, EM/IR, and LEC/Formality).
• Must-have: Demonstrated ability to own a block or subsystem in a small cross-functional team and meet tapeout milestones.
• Must-have: Effective cross-team communication with architects, RTL designers, and DFT engineers to resolve implementation issues.
• Nice-to-have: UPF/multi-voltage power domain experience, multi-clock/CDC-aware implementation, PLL/DLL integration, SoC interface IP integration (e.g. I3C, UART), and DFT-aware physical implementation (OCC/MBIST).
• Must-have: Ability to access U.S. export-controlled technology where required; employment may be contingent on citizenship/permanent residency or obtaining a U.S. export license.

Education Requirements

Not specified.

About the Company

Company: Tenstorrent

Headquarters: Austin, Texas, United States

Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.