Physical Design Engineer (PD/PnR)

Job Title

Physical Design Engineer (PD/PnR)

Role Summary

Implement block-level and top-level physical design for complex SoC projects, focusing on place-and-route, timing closure, low-power integration, and signoff. Work with RTL, DFT, power, and signoff teams to meet performance, power, and area (PPA) targets.

Experience Level

Mid-level — typically engineers with experience in block and top-level PnR flows (roughly 3–7 years of relevant experience).

Responsibilities

Primary delivery and technical responsibilities include:

• Perform block-level and top-level physical implementation using Synopsys Fusion Compiler.
• Drive floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure.
• Execute and analyze Static Timing Analysis (STA) across multiple corners and modes.
• Integrate and verify low-power features using UPF: isolation, level shifters, retention, and power domain checks.
• Support physical signoff activities including DRC, LVS, IR drop, and EM analysis.
• Collaborate with RTL, DFT, power, and signoff teams to resolve issues and reach PPA targets.

Requirements

Must-have technical skills and experience:

• Hands-on experience with Synopsys Fusion Compiler and PnR flows.
• Strong understanding of STA, timing closure, and multi-mode multi-corner (MMMC) methodologies.
• Experience with low-power implementation and verification flows (UPF-related flows preferred).
• Proficient scripting skills in Tcl, Perl, or Python for flow automation and debug.

Nice-to-have:

• Experience with advanced process nodes (7nm and below).
• Exposure to full-chip integration and signoff methodologies.
• Strong debugging and system-level problem-solving skills.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: CaritaTech

Engineering staffing and consulting firm providing placement and contract services for hardware, semiconductor, and embedded systems professionals, including roles in SoC/ASIC physical design and verification.