Physical Design Engineer II, Silicon Engineering

Job Title

Physical Design Engineer II, Silicon Engineering

Role Summary

Join the Starlink silicon engineering team to develop next-generation ASICs for space and ground infrastructure. Work cross-functionally with systems, firmware, architecture, design, validation and product engineering to take chips from RTL through GDSII and signoff.

This role focuses on physical implementation, timing closure, and methodology/automation improvements for production ASICs used in the Starlink network.

Experience Level

Mid-level. The role expects 3+ years of professional experience working on RTL-to-GDSII physical design or physical design flow development.

Responsibilities

Implement and close complex physical design projects and improve the physical implementation flow.

• Perform partition synthesis and full physical implementation steps: synthesis, floorplanning, power/ground grid generation, place-and-route, timing, noise, and physical verification.
• Execute signoff checks including static timing analysis (STA), electromigration, voltage drop, noise, and logic equivalency.
• Develop and maintain physical design methodologies and automation scripts to improve flow efficiency and robustness.
• Collaborate with ASIC designers to set timing, power, and area targets and evaluate RTL/design tradeoffs.
• Identify and resolve design, timing, and congestion issues; propose and drive corrective actions to closure.
• Run, debug, and fix signoff closure issues across STA, physical verification, EM/IR, and equivalency checks.

Requirements

Key technical requirements and desirable skills.

• Must-have: 3+ years working on RTL-to-GDSII physical design and/or physical design flow development.
• Must-have: Hands-on experience with physical implementation tasks (synthesis, floorplan, P/G, place & route, STA, signoff checks).
• Must-have: Proficiency with scripting for automation (Python, TCL, Bash/Makefile, Perl, or similar).
• Must-have: Practical experience using industry EDA tools and interpreting their results for timing, noise, and physical verification.
• Nice-to-have: Knowledge of deep sub-micron FinFET/CMOS physics, CMOS power/leakage behavior, and standard cell libraries.
• Nice-to-have: Familiarity with DFT concepts (scan, MBIST/LBIST) and their physical design impact; CMOS analog/physical design experience.
• Willingness to work extended hours and weekends when required to meet critical milestones.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.

About the Company

Company: SpaceX

Headquarters: Hawthorne, California, United States

SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.