Physical Design Engineer II

Job Title

Physical Design Engineer II

Role Summary

Member of Microsoft's Compute Silicon & Manufacturing Engineering team within Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE). Responsible for physical design and implementation of SOC blocks, from RTL through GDS, to support cloud infrastructure chips and production silicon.

Experience Level

Mid-level. Typically requires 2+ years of technical engineering experience (or equivalent) consistent with an Engineer II role.

Responsibilities

Deliver physical design execution and contribute to PD methodology and tool improvements while coordinating across design and manufacturing teams.

• Execute end-to-end physical design (synthesis through place-and-route) for small to medium SOC partitions, completing timing signoff, physical verification, EMIR, formal equivalence, and low-power verification.
• Design and implement clock construction and clock tree synthesis (CTS) strategies.
• Drive methodology exploration and optimization for SOC blocks to meet power, performance, and area goals.
• Implement RTL-to-GDS implementation tasks within the Physical Design domain.
• Coordinate with CAD, RTL/design, DFT, architecture, power & performance, technology, and manufacturing partners.
• Influence tools, flows, and methodologies using data-driven analysis.
• Communicate project status, schedules, and risks to cross-functional teams.
• Foster collaboration across teams to deliver manufacturable, high-quality silicon.

Requirements

Must-have technical skills and screening requirements are listed below; preferred skills follow.

• Must-have: 2+ years technical engineering experience or equivalent experience.
• Must-have: Practical experience executing PD flows through signoff (timing, physical verification, EMIR, formal equivalence, low-power verification).
• Must-have: Hands-on experience with clock construction and CTS for high-speed designs.
• Must-have: Experience implementing RTL-to-GDS for SOC partitions and coordinating cross-functional integration.
• Must-have: Strong collaboration and communication skills to work with CAD, PD methodology, RTL/design, architecture, and manufacturing teams.
• Must-have: Ability to meet Microsoft Cloud Background Check and export-control eligibility requirements.
• Preferred: Production silicon tape-outs in advanced foundry nodes.
• Preferred: Experience with low-power design methodology and PPA trade-offs for SOC/subsystem design.
• Preferred: Familiarity with multiple clock construction strategies and PD flow/methodology ownership.
• Preferred: Problem-solving and data-analysis skills; experience partnering with PD flow/CAD teams to resolve tool or flow issues.

Education Requirements

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (plus 1+ year technical engineering experience) OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (plus 2+ years technical engineering experience), OR equivalent practical experience. Candidates must also be able to provide proof of citizenship or lawful residency as required for export-controlled information access.

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.