Physical Design Engineer - Flow & Methodologies

Job Title

Physical Design Engineer - Flow & Methodologies

Role Summary

Design and own the physical-design (PD) methodology and RTL-to-GDSII flow for Etched's inference hardware. You will build automated flows, CAD infrastructure, and metrics that enable fast, repeatable PD across block and top-level projects.

This role partners with block owners, EDA vendors, and signoff teams to deliver production-ready flows, improve PPA, and reduce iteration time-to-results.

Experience Level

Mid-level. Preferred experience: 5–10+ years in physical design, PD methodology, or CAD engineering.

Responsibilities

Deliver and maintain production PD flows and the infrastructure that supports multiple design teams.

• Architect, build, and maintain automated RTL-to-GDSII flows from synthesis through place-and-route to signoff handoff.
• Automate run management, regressions, configuration release/version control, and flow regression infrastructure.
• Build and own CAD infrastructure: tool qualification/deployment, compute and license management, and job scheduling optimizations.
• Define reference flows, QoR targets, delivery checklists, and audit third-party PD service deliveries.
• Create block- and full-chip PG meshes and DRC‑clean floorplanning flows, and enable automated floorplan signoff checks.
• Drive PPA tuning and maintain timing correlation from pre-route through post-route and signoff tools.
• Instrument dashboards and metrics for timing, physical verification, utilization, and convergence across projects.
• Work with EDA vendors to evaluate and integrate new tool features and optimize flows.

Requirements

Core technical skills and domain experience required for the role. Candidates should be able to deliver production PD flows and automated CAD infrastructure.

• Must-have: 5–10+ years experience in PD or PD methodology/CAD.
• Must-have: Experience building and owning automated RTL-to-GDSII flows used by multiple block owners.
• Must-have: Experience creating block-level and full-chip PG mesh from design rules and EM/IR feedback.
• Must-have: Experience with DRC-clean floorplanning flows and automated checks.
• Must-have: Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) RTL-to-GDSII flows and integrating sign-off tools (PrimeTime, Tempus, Voltus, Pegasus, Calibre).
• Must-have: PPA tuning and timing correlation across pre-route, post-route, and signoff environments.
• Must-have: Strong Tcl and Python skills for flow development and automation.
• Must-have: Experience with back-end design on advanced process nodes (5nm and below) and UPF-based low-power methodology.
• Nice-to-have: Familiarity with modern ML/LLM architectures and AI programming tools.
• Nice-to-have: Experience optimizing compute farms and job schedulers for EDA workloads; startup experience.

Education Requirements

Not specified.

About the Company

Company: Etched

Headquarters: San Jose, CA, United States

Etched develops purpose-built AI inference ASICs and systems optimized for transformer models, aiming to deliver significantly higher performance, lower cost, and lower latency than GPUs. The company focuses on enabling applications like real-time video generation and advanced reasoning agents, and is backed by leading investors and engineers.