Physical Design Engineer (Engineer to Principal Level)
QualcommJob Title
Physical Design Engineer (Engineer to Principal Level)
Role Summary
Join Qualcomm's Digital ASIC Physical Design team to implement and deliver high-performance, low-power SoCs and IP blocks from synthesis through final tapeout. The team works across architecture, RTL, DFT, verification, CAD, and product engineering to achieve timing closure, power optimization, and design signoff.
This posting covers multiple career levels (Engineer through Principal) supporting GPU, multimedia, AI, compute, connectivity, modem, DDR, audio and other SoC programs.
Experience Level
Multiple levels available: Engineer through Principal. Typical experience guidance by level: Engineer ~2+ years; Senior Engineer ~4+ years; Staff Engineer ~8+ years; Senior Staff ~12+ years; Principal Engineer ~15+ years.
Responsibilities
Deliver physical implementation and signoff tasks for ASIC/SoC blocks; responsibilities scale with level and may include leadership, methodology definition, and cross-team coordination.
- Floorplanning, power planning, placement, CTS, routing, and physical verification.
- Timing analysis, static timing closure, and signal integrity analysis across modes and corners.
- Identify and resolve congestion, timing, power, and layout issues; implement ECOs as needed.
- Develop scripts and automation to improve productivity and implementation flows.
- Drive methodology improvements and scalable flows; mentor and guide junior engineers (mid-to-senior levels).
- Coordinate cross-functional alignment with Design, DFT, CAD, Verification, and Product teams; lead implementation for large subsystems at senior levels.
Requirements
Must-have technical skills and experience; preferred items noted separately.
- Proven experience with digital ASIC physical implementation and signoff (place & route, STA, CTS, routing).
- Experience with timing closure, power/performance/area tradeoffs, and design convergence across corners and modes.
- Linux/Unix development and engineering experience.
- Programming or scripting experience (Python, Tcl, Perl, Shell, or similar) for automation and flow development.
- Experience with static timing analysis tools and methodologies.
- Strong analytical, debugging, and problem-solving skills.
- Nice-to-have: hands-on use of Cadence Innovus and/or Synopsys Fusion Compiler; PrimeTime STA; RC extraction, signal integrity, cross-talk, EM/IR analysis; UPF/low-power implementation; DFT-aware implementation.
Education Requirements
Bachelor's, Master’s, or PhD in Science, Engineering, or a related technical field (examples given: Electrical Engineering, Computer Engineering, Computer Science) are cited as qualifying credentials. Job also accepts equivalent practical experience where indicated (degree + specified years OR equivalent experience combinations appear in the posting).
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
