Physical Design Engineer - DSP Team

Job Title

Physical Design Engineer - DSP Team

Role Summary

Responsible for physical implementation and convergence of DSP blocks, focusing on synthesis, placement, clock tree synthesis (CTS), and PPA (power, performance, area) optimization. This role works within ASICS Engineering to push performance while containing power and area.

Experience Level

Senior-level — the posting requests significant experience (notably 12+ years) in ASIC physical design, synthesis, or related work. Candidates should have a proven track record delivering complex block-level physical implementations.

Responsibilities

Core responsibilities include improving implementation flows, developing semi-custom techniques, and collaborating across teams to meet PPA targets.

• Update and optimize physical implementation flows to improve PPA.
• Develop and apply semi-custom design techniques to maximize utilization and performance.
• Extend and automate design methodologies via scripting to improve convergence and repeatability.
• Collaborate with logic and physical design teams and work independently with limited supervision.
• Communicate complex technical information clearly to varied audiences; influence design and implementation decisions.
• Perform creative problem solving for tasks without defined steps; apply advanced data analysis and interpretation.
• Use physical design tools to implement complex blocks and recommend protocol or implementation changes.
• Run advanced power checks across multiple blocks and recommend fixes when specifications are not met.

Requirements

Must-have technical skills and experience required for this role; preferred items listed separately.

• Extensive ASIC physical design experience (role expects significant senior-level experience; posting lists 12+ years in core qualifications).
• Strong proficiency in place-and-route, timing analysis, and physical verification flows.
• Experience with CAD tools such as Synopsys Fusion Compiler / DC, Cadence ICC2 / Innovus, or Genus.
• Solid understanding of logic optimization, clock structures, and power optimization for high-speed designs.
• Experience developing automation and scripting to improve design methodology and convergence.
• Demonstrated independent problem solving, creativity in process improvement, and ability to influence technical decisions.
• Strong verbal and written communication skills for technical audiences and leadership.

Nice-to-have:

• Experience with CPU or GPU design; extensive experience (e.g., 15+ years) is listed as preferred.
• Longstanding experience (10+ years) with architecture/design tools and scripting/programming for automation.

Education Requirements

The posting references degree-based minimums: a Bachelor's in Science, Engineering, or related field (baseline), with alternate experience mappings: BS +6 years, MS +5 years, or PhD +4 years of relevant ASIC design/verification/integration experience. Preferred fields include Electrical Engineering, Computer Engineering, or Computer Science. The posting also allows related fields or equivalent practical experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.