Physical Design Engineer — Die-to-Die Interface (RTL to GDSII)

Job Title

Physical Design Engineer — Die-to-Die Interface (RTL to GDSII)

Role Summary

Drive Die-to-Die (D2D) physical implementation and closure for multi-die/chiplet ASICs, owning the RTL-to-GDSII physical design flow from netlist to tapeout. Partner with full-chip and analog teams to deliver sign-off quality D2D interfaces.

This is a remote role open to applicants located in the United States.

Experience Level

Mid-level (3–7 years). The role prefers candidates with 5+ years of physical design experience at advanced nodes (7nm or below) and multiple successful tapeouts.

Responsibilities

Primary responsibilities for this role include leading D2D implementation and owning the full physical design flow:

• Lead D2D physical implementation and closure, taking high-speed D2D PHYs/controllers from netlist to tapeout.
• Own the RTL-to-GDSII flow: synthesis, floorplanning, place-and-route, CTS, optimization, and sign-off.
• Drive timing and verification including full STA (setup/hold) and timing closure.
• Perform SI analysis (crosstalk, IR drop) and achieve sign-off quality DRC/LVS.
• Develop and maintain physical design methodologies, flows, and automation scripts (Tcl, Python) focused on D2D routing and power grid design.
• Collaborate with full-chip/chiplet and analog PHY teams on LEF/LIB, constraints, integration, and debug.
• Apply EDA tools (Synopsys, Cadence, Mentor) for implementation, analysis, and verification.

Requirements

Must-have technical skills and qualifications:

• 5+ years of ASIC physical design experience at advanced nodes (7nm or below) with multiple tapeouts.
• Proven experience owning full-chip implementation and closure across synthesis, floorplanning, P&R, CTS, and sign-off.
• Experience with high-speed interfaces (D2D, PCIe, HBM, SerDes) and associated timing, SI, and PI challenges.
• Strong STA and constraint management skills for complex, high-speed designs.
• Proficient in scripting and automation for PD flows (Tcl, Python).
• Practical experience with Synopsys, Cadence, and Mentor tool suites for implementation and sign-off.
• Ability to collaborate across analog, digital, and full-chip teams to debug integration issues.
• Eligibility to access U.S. export-controlled technology; offers may be contingent on citizenship/permanent residency or ability to obtain required licenses.

Nice-to-have:

• Direct experience with multi-die/chiplet architectures and D2D routing strategies.
• Background in analog/PHY integration and model handoff (LEF/LIB).
• Experience optimizing power grids for high-speed interfaces.

Education Requirements

B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Tenstorrent

Headquarters: Austin, Texas, United States

Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.