Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Join a semiconductor SoC/ASIC team to perform RTL-to-GDSII physical implementation and signoff for advanced technology nodes. The role focuses on floorplanning, placement, CTS, routing, timing closure, power optimization, verification, and tapeout readiness.

Onsite in Santa Clara, CA; required five days per week in the office.

Experience Level

Mid-level — 5–15 years of relevant physical design experience.

Responsibilities

Primary responsibilities include implementation, verification, and signoff across block and full-chip flows.

• Perform floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification.
• Drive timing closure, congestion analysis, and power optimization for blocks and full-chip designs.
• Execute netlist-to-GDSII implementation and support tapeout readiness.
• Analyze and resolve setup/hold violations, signal integrity, IR drop, and EM issues.
• Collaborate with RTL, DFT, STA, and backend teams to converge designs and support ECO flows.
• Support low-power implementation techniques and UPF/CPF flows where applicable.

Requirements

Must-have skills and tools for immediate contribution; preferred items listed after.

• Hands-on experience with physical design flow from netlist to GDSII, including signoff.
• Experience with tools such as Cadence Innovus, Synopsys ICC2, PrimeTime, Tempus, and Calibre (or equivalents).
• Strong static timing analysis (STA) skills; knowledge of IR drop and EM analysis, DRC/LVS verification.
• Experience targeting advanced nodes (7nm/5nm/3nm) and handling tapeout flows.
• Proficient scripting in Tcl, Perl, or Python for automation and debug.
• Strong debugging, problem-solving, and cross-team communication skills.

Nice-to-have:

• Experience with low-power design methodologies.
• Prior tapeout experience on complex SoCs or high-speed designs.

Education Requirements

Not specified.

About the Company

Company: CaritaTech

Engineering staffing and consulting firm providing placement and contract services for hardware, semiconductor, and embedded systems professionals, including roles in SoC/ASIC physical design and verification.