Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Member of the physical design team responsible for design and analysis of 2.5D/3D integrated ASIC products. Work includes block and full-chip physical design, packaging, power distribution, clocking, thermal/cooling analysis, and signoff activities.

Collaborate with architecture and RTL teams to research and implement novel 3D integration concepts and to optimize designs for power, performance, and area.

Experience Level

Senior — 10+ years of physical design and verification experience (hands-on ASIC/SoC physical implementation and signoff).

Responsibilities

Key responsibilities include designing, analyzing, and delivering physical implementations for advanced multi-die products.

• Develop block-level and full-chip physical designs for 2.5D/3D products (floorplanning, placement, routing, integration).
• Perform and resolve DRC/LVS and PDV issues at block and full-chip level using ICV/Calibre or equivalent tools.
• Conduct IR/EM analysis and implement fixes to ensure reliability.
• Optimize designs for power, performance, and area in collaboration with RTL and architecture teams.
• Implement synthesis-driven physical design flows and timing closure tasks (STA-related work as needed).
• Design power distribution and clocking strategies and perform clock distribution analysis.
• Perform cooling and thermal analysis relevant to packaging and system integration.
• Automate and enhance flows using scripting (Tcl, Python) and tool integration.
• Lead integration and signoff activities across teams and supplier tools.

Requirements

Must-have and preferred skills for successful performance in the role.

Must-have:

• 10+ years of physical design/verification experience for ASICs/SoCs.
• Strong knowledge of block-level and full-chip physical verification methodology.
• Proven experience with block physical design, synthesis-driven flows, PDV and IR/EM analysis.
• Expertise resolving block and full-chip DRC and LVS issues with ICV or Calibre (or equivalent).
• Experience across the complete physical design flow through signoff.
• Proficient scripting skills (Tcl, Python) for flow automation and enhancements.
• Ability to collaborate with RTL teams to optimize designs for physical implementation.
• Knowledge of 2.5D or 3D packaging solutions and associated integration challenges.

Nice-to-have:

• Experience with full-chip floorplanning and large-scale integration.
• Deep knowledge of clock distribution networks and STA methodologies.
• Experience with cooling/thermal analysis for packaged systems.
• Familiarity with Synopsys tool suite.

Education Requirements

Not specified.

About the Company

Company: Cerebras

Headquarters: Sunnyvale, CA, USA

Developer of wafer-scale AI accelerators, Cerebras designs the Wafer Scale Engine (WSE)—one of the world’s largest AI chips—to deliver high-speed training and inference solutions for model labs, enterprises, and AI-native startups.