Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Work on physical implementation of ASIC blocks and top-level designs, owning the flow from netlist handoff to tapeout. The role focuses on timing closure, low-power techniques and physical verification within a collaborative SOC design team.

Experience Level

Mid-level. Typical guidance in the posting: BSEE with 6+ years experience or MSEE with 3+ years experience (years guidance only).

Responsibilities

Deliver physical design for blocks or top-level SOCs and ensure manufacturable, timing-closed layouts.

• Own physical design flow from netlist handoff through floorplanning, place-and-route, clock tree synthesis, timing closure and physical verification to GDSII tapeout.
• Implement and validate low-power techniques and optimizations.
• Analyze and mitigate signal integrity and power delivery issues (crosstalk, IR drop, electromigration).
• Develop automation and productivity scripts (TCL, Perl) for design and signoff tasks.
• Collaborate closely with logic designers and cross-functional teams to integrate complex SOC blocks.
• Prepare technical presentations and communicate design status and risks to stakeholders.

Requirements

Must-have technical skills and attributes:

• Proven physical design experience covering floorplanning, placement, routing, CTS, timing closure and physical verification.
• Hands-on experience with 45nm or 28nm technology nodes.
• Experience applying low-power design techniques in physical implementation.
• Proficient scripting skills in TCL and Perl for automation.
• Ability to analyze crosstalk, IR drop and electromigration and implement fixes.
• Strong communication, presentation skills, and attention to detail; organized and methodical.

Education Requirements

BSEE with 6+ years of relevant experience or MSEE with 3+ years of relevant experience; degrees in Electrical Engineering, Computer Engineering, Computer Science or a closely related technical field, or equivalent practical experience.

About the Company

Company: Oso Semiconductor

Headquarters: Mountain View, CA, United States

Early-stage fabless semiconductor startup developing mmWave beamforming RFICs that deliver 2–4x power reduction for phased array systems across SATCOM, 5G, and radar. Founded by UC Berkeley PhDs, the company has raised Series A funding and works with defense and commercial customers on full-custom mmWave front-end and beamformer chips.