Physical Design Engineer - Block Level, Subsystem Implementation

Job Title

Physical Design Engineer - Block Level, Subsystem Implementation

Role Summary

Own block-level and subsystem physical implementation from RTL synthesis through GDSII sign-off. Drive timing, power, and PPA optimization for blocks and subsystems and collaborate closely with RTL designers to improve upstream deliverables and integration.

This role is based in the Austin office with regular in-person collaboration in San Jose (initially ~2 weeks/month, later ~1 week/month).

Experience Level

Mid-level — typically 5 to 10+ years of relevant physical design experience preferred.

Responsibilities

Primary responsibilities include:

• Own block-level and subsystem physical design end-to-end: floorplanning, synthesis, placement, clock tree synthesis, routing through GDSII.
• Drive block-level timing closure across corners and modes; develop constraints, debug STA, and implement functional/timing ECOs.
• Achieve signoff across EM, IR drop, RC extraction/correlation, and physical verification (DRC, LVS, antenna).
• Generate abstracts, views, and timing budgets for hierarchical integration into top-level designs.
• Provide actionable physical-design feedback to RTL designers to improve PPA and the RTL-to-GDSII flow.
• Continuously improve PPA of owned blocks and document flow improvements and best practices.
• Supervise and accept responsibility for physical design work delivered by third-party services.

Requirements

Must-have:

• 5–10+ years of hands-on physical design experience and familiarity with RTL-to-GDSII flows and methodology.
• Experience with back-end design and timing closure on advanced process nodes (5 nm and below).
• Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) flows and sign-off tools (PrimeTime, Tempus, Voltus, etc.).
• Knowledge of UPF-based low-power design, power verification, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, EM/antenna analysis.
• Scripting ability for flow automation and debug (Tcl, Python, or Perl).

Nice-to-have:

• Familiarity with modern ML and LLM model architectures and how hardware PPA interacts with inference workloads.
• Startup experience or comfort working in fast-paced, cross-disciplinary teams.

Education Requirements

Not specified.

About the Company

Company: Etched

Headquarters: San Jose, CA, United States

Etched develops purpose-built AI inference ASICs and systems optimized for transformer models, aiming to deliver significantly higher performance, lower cost, and lower latency than GPUs. The company focuses on enabling applications like real-time video generation and advanced reasoning agents, and is backed by leading investors and engineers.