Physical Design Engineer - Block Level, Subsystem Implementation

Job Title

Physical Design Engineer - Block-level / Subsystem Implementation

Role Summary

Own block- and subsystem-level physical implementation from RTL synthesis through GDSII sign-off. Work closely with RTL designers and backend teams to drive PPA, timing closure, signoff, and hierarchical integration for inference-focused hardware.

Experience Level

Mid-level. Target candidates with roughly 5–10 years of physical design experience; equivalent practical experience considered.

Responsibilities

Key responsibilities include end-to-end block/subsystem physical implementation and cross-team integration.

• Lead block- and subsystem-level physical implementation: floorplanning, synthesis, placement, CTS, routing through GDSII.
• Drive timing closure across corners and modes: constraint development, STA debug, and timing ECOs.
• Achieve signoff across EM, IR drop, RC extraction/correlation, and physical verification (DRC, LVS, antenna).
• Produce abstracts, views, and timing budgets for hierarchical integration into top-level design.
• Provide actionable physical-design feedback to RTL teams to improve PPA and implement iterative improvements to the RTL-to-GDSII flow.
• Manage and qualify work performed by third-party physical-design services, owning quality and closure of delivered blocks.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

• 5+ years of block/subsystem physical design experience (experience statement in posting indicates ~5–10 years).
• Experience with RTL-to-GDSII flows and backend design methodology, including synthesis, placement, CTS, routing, and signoff.
• Hands-on experience on advanced process nodes (5nm and below).
• Familiarity with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) flows and sign-off tools (PrimeTime, Tempus, Voltus, etc.).
• Experience with UPF-based low-power methodology, power verification, scan insertion/ATPG, formal verification, IR drop, EM, and antenna analysis.
• Scripting for flow automation and debug (Tcl, Python, or Perl).
• Proven ability to debug timing/PPA issues and implement functional/timing ECOs.

Nice-to-have:

• Familiarity with modern ML/LLM model architectures and tools.
• Startup experience or comfort working in a fast-paced, in-person engineering environment.

Education Requirements

Not specified.

About the Company

Company: Etched

Headquarters: San Jose, CA, United States

Etched develops purpose-built AI inference ASICs and systems optimized for transformer models, aiming to deliver significantly higher performance, lower cost, and lower latency than GPUs. The company focuses on enabling applications like real-time video generation and advanced reasoning agents, and is backed by leading investors and engineers.