Physical Design Engineer — Block-Level & Subsystem Implementation
EtchedJob Title
Physical Design Engineer — Block-Level & Subsystem Implementation
Role Summary
Own block-level and subsystem physical design from RTL synthesis through GDSII sign-off. Drive block-level and subsystem PPA (power, performance, area) optimization and ensure clean hierarchical integration into top-level designs.
Work closely with RTL designers, manage sign-off across timing, power, and physical verification domains, and supervise outsourced physical design deliveries when needed.
Experience Level
Mid-level. Prefer candidates with roughly 5–10+ years of relevant physical-design experience.
Responsibilities
Primary responsibilities for this role include:
- Own end-to-end block/subsystem physical design: floorplanning, synthesis, placement, clock-tree synthesis, routing, and GDSII sign-off.
- Drive block-level timing closure across corners and modes: constraint development, STA debugging, and functional/timing ECOs.
- Achieve sign-off for EM/IR, RC extraction and correlation, and physical verification (DRC, LVS, antenna).
- Produce abstracts, timing views, and timing budgets for hierarchical integration.
- Collaborate with RTL designers to provide actionable PD feedback and improve PPA.
- Continuously improve RTL-to-GDSII flow and contribute reusable methodology improvements.
- Manage and be accountable for physical-design work performed by third-party vendors.
Requirements
Minimum technical skills and experience required for the role.
Must-have:
- 5+ years of hands-on physical-design experience, covering RTL-to-GDSII flows and block-level sign-off.
- Experience with back-end design and timing closure on advanced process nodes (5nm and below).
- Familiarity with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) RTL-to-GDSII flows and sign-off toolsets (PrimeTime, Tempus, Voltus, etc.).
- Practical experience with UPF-based low-power methodology, power verification, IR/EM/antenna analysis, RC extraction, and DRC/LVS sign-off.
- Strong STA, constraint development, and ECO implementation skills.
- Scripting for flow automation and debug (Tcl, Python, or Perl).
- Proven ability to supervise external vendors and validate delivered blocks to quality and closure requirements.
Nice-to-have:
- Familiarity with modern ML and LLM model architectures.
- Additional programming experience in Python or similar for tooling and automation.
- Prior startup experience or demonstrated ability to work in fast-paced environments.
Education Requirements
Not specified.
About the Company
Company: Etched
Headquarters: San Jose, CA, United States
Etched develops purpose-built AI inference ASICs and systems optimized for transformer models, aiming to deliver significantly higher performance, lower cost, and lower latency than GPUs. The company focuses on enabling applications like real-time video generation and advanced reasoning agents, and is backed by leading investors and engineers.
