Physical Design Engineer - Bengaluru

Job Title

Physical Design Engineer - Bengaluru

Role Summary

Join the physical design team to perform block and full-chip physical implementation for a wafer-scale AI accelerator. The role covers synthesis, place-and-route, timing closure, physical verification and full-chip integration while working closely with RTL teams.

This is a hands-on engineering role focused on delivering sign-off quality blocks and supporting integration for a large-scale, performance- and power-sensitive chip architecture.

Experience Level

Senior — requires 7+ years of physical design or verification experience.

Responsibilities

Primary responsibilities include:

• Perform synthesis, place-and-route, timing analysis and block-level closure.
• Support full-chip floorplanning and integration of blocks into wafer-scale designs.
• Drive physical verification (DRC/LVS) and resolve full-chip and block issues.
• Perform IR/EM analysis, mitigation and sign-off activities.
• Collaborate with RTL teams to optimize designs for PPA (power, performance, area).
• Develop and enhance flows and automation using scripting (Tcl, Python).
• Lead post-ramp tasks and mentor others on physical design practices.

Requirements

Must-have technical skills and experience:

• 7+ years of experience in physical design or verification of complex ASIC blocks/systems.
• Proven experience with block/subsystem timing closure and full-chip timing sign-off.
• Strong knowledge of block-level and full-chip physical verification methodology and PDV workflows.
• Experience resolving DRC/LVS issues using ICV or Calibre.
• Expertise in IR/EM analysis and remediation.
• Practical experience in floorplanning and block integration for large designs.
• Proficiency in scripting (Tcl, Python) to improve and automate flows.
• Ability to work closely with RTL teams and assume a leadership role after ramp-up.

Nice-to-have:

• Familiarity with Synopsys tool suite and end-to-end physical design flow.
• Background in synthesis and static timing analysis (STA).

Education Requirements

Degrees preferred: B.S. or M.S. in Electrical Engineering; Ph.D. in Electrical Engineering is also listed as preferred. (Relevant equivalent experience acceptable where applicable.)

About the Company

Company: Cerebras

Headquarters: Sunnyvale, CA, USA

Developer of wafer-scale AI accelerators, Cerebras designs the Wafer Scale Engine (WSE)—one of the world’s largest AI chips—to deliver high-speed training and inference solutions for model labs, enterprises, and AI-native startups.