Physical Design Engineer
AkeanaJob Title
Physical Design Engineer
Role Summary
Work on SoC and processor physical design within a small startup team. You will own significant portions of the chip physical design implementation and verification, collaborating closely with RTL and system architects to meet timing, area and power targets.
Role is based in Santa Clara, CA and involves end-to-end physical design tasks from synthesis through signoff.
Experience Level
Mid-level. No specific years of experience specified.
Responsibilities
Primary responsibilities include:
- Implement and maintain physical-design flows, including synthesis, place & route (P&R), and timing closure.
- Apply and verify power-saving techniques and power-aware design methodologies.
- Own full-chip physical verification for hierarchical designs and drive signoff activities.
- Collaborate with RTL designers, verification, and system teams to resolve issues and meet project milestones.
- Deliver signoff-ready layouts and documentation for assigned chip blocks.
Requirements
Must-have:
- Strong background in physical design and PD flows (synthesis, P&R, timing closure).
- Experience with power-reduction techniques and power-aware design practices.
- Experience owning full-chip physical verification on hierarchical chips.
- Ability to take ownership of substantial chip blocks within a small-team/startup environment.
- Good collaboration and communication skills across engineering teams.
Nice-to-have:
- Experience with SoC and processor designs.
- Previous experience at semiconductor companies or startups.
Education Requirements
Not specified.
About the Company
Company: Akeana
Headquarters: Santa Clara, CA, USA
Akeana is a start-up specializing in processor design, with a team experienced in developing state-of-the-art products. Their expertise spans multiple architectures, including Risc-V, ARM, and x86, with backgrounds from prominent companies in the semiconductor industry. Funded by top-tier venture capitalists and industry leaders, Akeana focuses on innovative RTL design and micro-architecture development.
