Physical Design Engineer, AI Accelerator IP
TenstorrentJob Title
Physical Design Engineer, AI Accelerator IP
Role Summary
Responsible for end-to-end physical implementation of AI accelerator and IP blocks, from synthesis through place-and-route, timing closure, and GDSII signoff. Deliver hardened, PPA-validated IP for external licensees on advanced process nodes.
Hybrid role collaborating with architecture, RTL, and chiplet integration teams. Based out of Toronto, ON; Austin, TX; or Belgrade, Serbia.
Experience Level
Mid-level. Typical candidates have 5+ years of block-level or IP-centric physical design experience; the company may consider various seniorities during interview and align offers to assessed level.
Responsibilities
Primary responsibilities include delivering high-quality IP implementations that meet PPA and schedule targets.
- Execute synthesis, floorplanning, place-and-route, clock tree synthesis, and timing closure for IP blocks.
- Develop and verify power grid, UPF-based low-power strategies, multi-Vt implementation, and voltage scaling.
- Perform static timing analysis (STA), logical equivalence checking (LEC), and signoff-quality verification.
- Prepare and deliver IP integration collateral: LEF/DEF, timing and power models, GDS, and signoff reports.
- Work closely with RTL owners to close critical paths and meet power budgets.
- Port the same block across process nodes, foundries, and PPA targets for multi-variant IP delivery.
- Ensure tapeout readiness and maintain rigorous signoff quality for customer-facing IP.
Requirements
Must-have skills, tools, and experience for successful candidates. Education details are summarized under Education Requirements below.
- 5+ years of block-level or IP-centric physical design experience, including tapeouts.
- Proven experience with industry-standard EDA tools such as Innovus, ICC2/FusionCompiler, and PrimeTime.
- Proficiency with scripting for automation and flow integration, e.g. Tcl and Python; Perl experience a plus.
- Deep practical knowledge of advanced-node challenges and signoff methodologies (STA, LEC).
- Experience building robust floorplans, power distribution networks, pin placement, and clocking strategies.
- Attention to detail for producing customer-ready IP integration deliverables and signoff artifacts.
- Nice to have: prior experience porting IP across foundries/nodes and delivering multi-variant PPA targets.
- Note: Employment may be contingent on eligibility to access U.S. export-controlled technology; offers may be affected by citizenship or residency status.
Education Requirements
Degree required: BS, MS, or PhD in Electrical Engineering, Electrical and Computer Engineering, Computer Engineering, Computer Science, or a closely related technical field. The posting indicates candidates typically have 5+ years of block-level or IP-centric physical design experience through tapeout.
About the Company
Company: Tenstorrent
Headquarters: Austin, Texas, United States
Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.
