Job Title
Physical Design Engineer
Role Summary
The Physical Design Engineer will work on ASIC implementation of DSP cores, supporting the flow from RTL handoff through physical implementation and tapeout. The role involves hands-on work in timing closure, power/performance/area (PPA) optimization, and physical verification under the guidance of senior engineers.
This is an early-career position on the DSP Physical Design team in Markham, collaborating with architecture, RTL, verification, DFT, and methodology teams to deliver silicon-ready designs.
Experience Level
Entry-level / Early-career — 6 months to 2 years of relevant experience (including internships or co-op experience).
Responsibilities
Key day-to-day tasks include implementing and closing designs, running analyses, and automating flows to improve productivity.
- Contribute to ASIC physical design from netlist to GDSII under senior guidance.
- Support floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification.
- Perform timing analysis, debug timing and congestion issues, and implement ECOs.
- Participate in PPA analysis and optimization efforts.
- Collaborate with RTL, DFT, verification, and methodology teams to resolve design issues.
- Develop scripts and automation to improve engineering productivity and design quality.
Requirements
Concise list of must-have and nice-to-have qualifications.
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Must-have: 6 months to 2 years of experience in ASIC Physical Design, Digital Design, VLSI, or a related semiconductor domain (including internships or co-op).
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Must-have: Strong fundamentals in VLSI and digital design: combinational and sequential logic, FSMs, clocking concepts, and timing analysis.
- Basic understanding of ASIC design flow from RTL to GDSII and familiarity with physical design concepts (floorplanning, placement, CTS, routing, timing analysis, physical verification).
- Exposure to industry-standard EDA tools for synthesis, implementation, timing analysis, or verification.
- Basic scripting skills (Python, Tcl, Perl, or Shell) and ability to develop simple automation.
- Strong analytical, debugging, problem-solving, communication, and teamwork skills.
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Nice-to-have: Familiarity with Verilog/SystemVerilog, STA, DFT fundamentals, low-power design concepts, experience with automation tools or AI-assisted engineering tools, and prior project or internship work in VLSI/Physical Design.
Education Requirements
Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, Science, or a related technical field; equivalent practical experience is acceptable.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.

Date Posted: 2026-08-05