Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Contribute to backend physical implementation of FPGA/SoC blocks and subsystems from netlist through sign-off. Work with RTL, architecture, DFT, CAD/EDA, and verification teams to resolve implementation challenges and deliver tape-out quality designs.

Experience Level

Mid-level. The posting specifies a minimum of 4+ years of industry experience in physical design or SoC/ASIC backend design.

Responsibilities

Execute block- and subsystem-level physical implementation tasks and collaborate across engineering teams to meet PPA and schedule goals.

• Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, ECOs, extraction, and physical sign-off activities.
• Analyze and optimize designs for timing, power, and area (PPA).
• Run static timing analysis, identify critical paths, and work with designers to close timing.
• Debug placement, congestion, clocking, routing, timing, and design-constraint issues.
• Support physical verification (DRC, LVS) and help resolve sign-off issues.
• Support block-level integration: constraints, pin placement, timing interfaces.
• Develop basic automation and scripts to improve productivity.
• Participate in design reviews, documentation, and process improvement.

Requirements

Must-have technical skills and tools experience (degree and minimum years are listed under Education Requirements).

• Hands-on experience with digital ASIC/SoC physical implementation flows (floorplanning, placement, CTS, routing, ECOs, sign-off).
• Experience with industry EDA tools such as Synopsys IC Compiler II, Fusion Compiler, PrimeTime, Cadence Innovus, or equivalents.
• Practical static timing analysis and timing-closure experience (analyzing reports, resolving setup/hold violations).
• Experience working with physical-design constraints (clocks, timing, placement, design rules).
• Ability to debug implementation issues: timing violations, congestion, routing, and DRC/LVS findings.
• Basic scripting/automation skills (Tcl, Python, Perl, Shell) to automate repetitive tasks.

Nice-to-have:

• Experience with advanced process nodes (16nm, 10nm, 7nm, 5nm or below) or FPGA device implementation.
• Familiarity with FPGA architectures, routing fabrics, CLBs, I/O structures, and hierarchical/full-chip flows.
• Low-power design experience (clock gating, power domains, power intent).
• Knowledge of power integrity (IR drop, EM) and signal integrity considerations.
• Exposure to physical-design automation or AI/ML-assisted optimization tools.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline is required; a Master’s degree is preferred. The posting specifies a minimum of 4+ years of industry experience in physical design or SoC/ASIC backend design.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.