Physical Design Engineer
Oso SemiconductorJob Title
Physical Design Engineer
Role Summary
Implement and own physical design tasks at block and top level for complex SoCs, focusing on floorplanning, place-and-route, clock tree synthesis, timing closure and physical verification. Collaborate closely with logic designers and verification teams to deliver tapeout-quality layouts while applying low-power techniques.
Experience Level
Mid-level. The posting specifies BSEE with 6+ years related experience or MSEE with 3+ years; typical candidates will have roughly 3–6+ years of relevant physical design experience.
Responsibilities
The role owns the full physical design flow and drives closure to tapeout.
- Own physical implementation from netlist handoff to GDSII/tapeout: floorplanning, placement, routing, CTS, timing closure, and physical verification.
- Analyze and mitigate crosstalk, IR drop, and electromigration issues.
- Develop automation and productivity scripts (TCL, Perl) for design and signoff flows.
- Apply low-power techniques during implementation and collaborate on power-aware design decisions.
- Work closely with logic designers and cross-functional teams to integrate RTL and physical constraints.
Requirements
Must-have skills and experience for immediate contribution (education requirements are listed separately below).
- Hands-on physical design experience across the full flow (netlist to tapeout).
- Experience with 45nm or 28nm process technologies.
- Practical experience with low-power implementation techniques.
- Proficient scripting skills in TCL and Perl for automation.
- Strong communication, presentation, organizational and attention-to-detail skills.
Education Requirements
Requires a Bachelor of Science in Electrical Engineering (BSEE) with 6+ years related experience, or a Master of Science in Electrical Engineering (MSEE) with 3+ years related experience. No other degrees, certifications, or equivalent-experience language was specified in the source.
About the Company
Company: Oso Semiconductor
Headquarters: Mountain View, CA, United States
Early-stage fabless semiconductor startup developing mmWave beamforming RFICs that deliver 2–4x power reduction for phased array systems across SATCOM, 5G, and radar. Founded by UC Berkeley PhDs, the company has raised Series A funding and works with defense and commercial customers on full-custom mmWave front-end and beamformer chips.
