Physical Design Engineer
eInfochipsJob Title
Physical Design Engineer
Role Summary
Work on physical implementation and signoff for assigned ASIC partitions, executing synthesis, place-and-route (PnR), static timing analysis (STA), and physical verification to meet project schedules and design goals.
Collaborate closely with architects, RTL designers, DFT engineers, and EDA vendors. This is a fully on-site role based in San Jose, CA.
Experience Level
Level: Senior - 7+ years of hands-on physical design and implementation experience.
Responsibilities
Primary responsibilities include implementation, verification, and coordination to achieve signoff for assigned blocks.
- Execute synthesis, place-and-route, and STA for assigned partitions to meet timing, area, and power targets.
- Drive EM/IR closure, logical equivalence checking (LEC), and physical verification signoff for partitions.
- Coordinate with architects, RTL, DFT, and methodology owners to resolve implementation and signoff issues.
- Apply low-power design techniques and timing convergence strategies to meet aggressive schedules.
- Identify and remediate physical-design challenges early to enable efficient iteration and convergence.
- Contribute to refinement of physical design methodologies (synthesis, PnR, EMIR, PDN, LEC).
- Troubleshoot flow issues and liaise with EDA vendors to resolve tool or methodology problems.
Requirements
Must-have technical skills and experience for immediate contribution.
- 7+ years of hands-on experience in physical design and implementation, including synthesis, PnR, timing convergence, and physical verification.
- Proficiency with EDA tools such as Innovus, Tempus, and Quantus and a deep understanding of physical design flows.
- Experience with System-on-Chip (SoC) design and integration activities.
- Expertise with sub-7nm process node implementation and related challenges.
- Strong TCL scripting skills to build custom flows and methodologies on standard EDA tools.
- Proven ability to meet tight schedules and implement low-power design techniques.
- Experience driving EM/IR closure, PDN considerations, and LEC/physical verification signoff.
- Ability to troubleshoot flows and collaborate with EDA vendors and methodology owners.
Nice-to-have:
- Experience refining or owning implementation/physical design methodology and automation.
- Familiarity with Cadence and Synopsys tool ecosystems beyond the tools listed above.
Education Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
About the Company
Company: eInfochips
Headquarters: Bengaluru, India
eInfochips is a product engineering and semiconductor design services company offering embedded software, SoC design and verification, testing, and IoT solutions. It operates as part of Arrow Electronics, serving clients across industries worldwide.
