Physical Design Engineer
Implement physical design for ASIC blocks and top-level SoC, focusing on timing closure and low-power techniques. The role is part of a chip-design team working closely with logic designers through to tapeout.
Mid-level: typically 3β6+ years of hands-on physical design experience depending on background.
Primary responsibilities include implementing and validating physical design flows and automating tasks.
Must-have technical skills and experience.
Bachelor of Science in Electrical Engineering (BSEE) with 6+ years related experience, or Master of Science in Electrical Engineering (MSEE) with 3+ years related experience. Fields: Electrical Engineering or closely related technical disciplines.
Company: Oso Semiconductor
Headquarters: Mountain View, CA, United States
Early-stage fabless semiconductor startup developing mmWave beamforming RFICs that deliver 2β4x power reduction for phased array systems across SATCOM, 5G, and radar. Founded by UC Berkeley PhDs, the company has raised Series A funding and works with defense and commercial customers on full-custom mmWave front-end and beamformer chips.
