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Physical Design Engineer

Oso Semiconductor
August 04, 2026
Full-time
On-site
California, US
Physical Design Jobs, Level - Mid-Career

Job Title

Physical Design Engineer

Role Summary

Implement physical design for ASIC blocks and top-level SoC, focusing on timing closure and low-power techniques. The role is part of a chip-design team working closely with logic designers through to tapeout.

Experience Level

Mid-level: typically 3–6+ years of hands-on physical design experience depending on background.

Responsibilities

Primary responsibilities include implementing and validating physical design flows and automating tasks.

  • Own physical design from netlist handoff to GDS/tapeout: floorplanning, placement & routing, clock tree synthesis, timing closure, and physical verification.
  • Analyze and mitigate crosstalk, IR drop, and electromigration issues.
  • Implement low-power design techniques and signoff strategies.
  • Develop automation and productivity scripts (TCL, Perl) for the physical design flow.
  • Collaborate closely with logic designers and other cross-functional teams during integration.

Requirements

Must-have technical skills and experience.

  • Hands-on physical design skills across the full flow: floorplanning, place & route, CTS, timing closure, physical verification.
  • Experience with 45nm or 28nm process technologies.
  • Experience applying low-power techniques in physical design.
  • Proficiency scripting in TCL and Perl for automation.
  • Strong communication, presentation, and organizational skills; detail oriented.

Education Requirements

Bachelor of Science in Electrical Engineering (BSEE) with 6+ years related experience, or Master of Science in Electrical Engineering (MSEE) with 3+ years related experience. Fields: Electrical Engineering or closely related technical disciplines.


About the Company

Company: Oso Semiconductor

Headquarters: Mountain View, CA, United States

Early-stage fabless semiconductor startup developing mmWave beamforming RFICs that deliver 2–4x power reduction for phased array systems across SATCOM, 5G, and radar. Founded by UC Berkeley PhDs, the company has raised Series A funding and works with defense and commercial customers on full-custom mmWave front-end and beamformer chips.

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Date Posted: 2026-08-02