Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Perform physical design implementation for custom IP and SoC from RTL to GDS, delivering manufacturable design databases. The role sits in Intel's Central Engineering Group (CEG) and supports product enablement, custom ASIC work, and foundry enablement.

Primary responsibilities include implementation, verification, optimization, and methodology improvements for timing, power, and layout signoff.

Experience Level

Senior — requires extensive experience; the posting requests 10+ years of ASIC/SoC implementation experience.

Responsibilities

The role covers end-to-end physical design flow and signoff activities. Key responsibilities include:

• Implement physical design from RTL to GDS, producing manufacturing-ready design databases.
• Execute synthesis, placement and routing, clock tree synthesis, floorplanning, and DFT integration.
• Perform static timing analysis, power and noise analysis, reliability checks, and layout verification.
• Conduct signoff activities: formal equivalence, timing signoff, power integrity, and electrical rule checking.
• Analyze results, identify violations, and recommend fixes for current and future architectures.
• Optimize designs for power, frequency, and area; contribute to methodology and flow automation improvements.

Requirements

Must-have technical skills and experience; preferred items listed where noted.

• 10+ years of experience in complex ASIC/SoC implementation (physical design and signoff).
• Experience designing and implementing complex blocks such as CPUs, GPUs, media blocks, and memory controllers.
• Strong experience with SystemVerilog and SoC development environments.
• Proficient scripting skills (Perl, Tcl, Python) for flow automation.
• Expertise in timing closure, physical clock design, multi-power-domain analysis, placing, routing, and DFT using industry EDA tools.
• Understanding of hardware validation techniques and signoff criteria.
• Knowledge of industry-standard protocols (PCIe, USB, DDR) — preferable.
• Low-power implementation/UPF and formal verification experience — preferable.

Education Requirements

B.Tech or M.Tech degree listed in the posting. The posting specifies 10+ years of related ASIC/SoC implementation experience; no additional certifications or fields of study were specified.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.