Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Member of the HIPD SAM physical design team responsible for end-to-end physical implementation and analog layout for Intel client, server and ASIC hard‑IP portfolios and advanced testchips.

Deliver RTL-to-GDS physical design, drive timing/power/area optimization, and improve methodologies and automation to meet performance and sign‑off requirements.

Experience Level

Mid-level. Typical experience ranges from ~4 to 6+ years depending on degree (see Education Requirements for details).

Responsibilities

Core responsibilities include executing full physical implementation, verification, and methodology improvement.

• Implement designs from RTL/Netlist through GDSII: synthesis, placement, routing, clock tree synthesis, floorplanning.
• Perform verification and sign‑off: formal equivalence, layout verification, electrical rule checking, static timing analysis, power integrity checks.
• Identify and resolve timing, power, and layout violations; provide architecture and implementation recommendations.
• Optimize designs for power, frequency, and area using industry EDA tools.
• Develop and improve physical design methodologies, automation flows, and processes.
• Define constraints for hierarchical integration and apply floorplanning concepts across multiple power domains.
• Collaborate with cross‑functional teams to meet quality, performance, and sign‑off criteria.

Requirements

Must-have technical skills and experience; degree requirements are summarized under Education Requirements below.

• Proven experience with RTL-to-GDS implementation flows using industry-standard EDA tools (synthesis, place & route, DFT flows).
• Advanced timing methodology knowledge and hands-on timing convergence experience.
• Practical experience with low-power design techniques and analysis of multiple power domains.
• Hands-on layout verification and familiarity with sign‑off criteria.
• Proficiency in scripting (Perl, TCL, Python) to automate flows and improve efficiency.
• Strong problem-solving skills and the ability to recommend architectural or implementation changes to resolve violations.
• Good communication and collaboration skills for cross-functional integration.

Nice-to-have:

• Experience with high-speed digital design techniques and sub-micron CMOS processes.
• Familiarity with hardware description languages (Verilog/SystemVerilog) and computer architecture concepts.
• Leadership or mentorship experience and history of delivering complex design projects.

Education Requirements

Minimum qualifications specify degree-plus-experience: Bachelor's degree in Electrical Engineering, Electronics Engineering or related field with 6+ years experience; OR Master's in Electrical Engineering, Microelectronics or VLSI with 4+ years; OR PhD with 2+ years. Fields referenced include Electrical/Electronics Engineering, Microelectronics, and VLSI. (Equivalent practical experience matching these experience levels is treated in the posted minimum qualifications.)

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.