Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Responsible for physical design implementation of ultra-high-performance, low-power data‑processing ASICs. Work within the core physical design (PD) team to floorplan, optimize PPA (performance, power, area), close timing at very high frequencies, and automate PD flows.

Collaborate with RTL designers, verification, and cross-functional teams to meet project milestones and delivery timelines.

Experience Level

Mid-level — more than 5 years of experience in high-performance semiconductor design is required.

Responsibilities

Primary responsibilities include:

• Implement ultra-high-performance, low-power processor SoC blocks using industry PD flows.
• Collaborate with RTL designers to achieve PPA targets and recommend trade-offs.
• Perform floor-planning and experiment with placement and routing techniques to improve PPA.
• Drive timing closure for very high-frequency designs; perform hand placement when needed.
• Define low-latency / low-skew clock tree methodology and power grid structures to meet EM/IR requirements.
• Write scripts and automate PD flows to improve turnaround and regression throughput.

Requirements

Key technical and behavioral requirements. Must-haves are listed first; nice-to-haves follow.

• Must-have: Strong experience in logic synthesis, timing analysis, floor-planning, and prototyping for high-performance ASICs.
• Proven experience implementing PD for advanced nodes, including timing closure at very high frequencies.
• Practical knowledge of Verilog and the full ASIC design flow.
• Experience with flow automation using Perl, Tcl, or Python and developing PD methodologies.
• Hands-on experience with Cadence Innovus on 7nm or smaller process nodes.
• Effective communication and collaboration skills to work with a global design team and meet project milestones.
• Nice-to-have: Background in computer architecture; experience mentoring junior engineers; familiarity with synthesizable RTL constructs (flops, FIFOs, CDC); knowledge of protocols such as PCIe, Ethernet (100G+), and DDR4; ability to create regression scripts for grid job submission.

Education Requirements

BS or MS degree in Electrical Engineering or Computer Science.

About the Company

Company: Tachyum

Headquarters: Sunnyvale, CA, USA

Tachyum develops Prodigy, a universal processor that combines CPU, GPU, and TPU capabilities to deliver high-performance, energy-efficient computing for AI, HPC, and cloud data centers. The company focuses on ultra-low power, hyperscale deployments and operates offices in the United States and Slovakia.