Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

The Physical Design Engineer will perform block- and/or top-level physical implementation for next-generation FPGA products, working with architecture, RTL, DFT, timing, power, CAD, and verification teams to deliver manufacturable silicon.

This role focuses on floorplanning, placement, CTS, routing, signoff preparation, and automation to improve physical design productivity.

Experience Level

Entry-level (2+ years industry experience in physical design or ASIC/SoC backend implementation).

Responsibilities

Primary responsibilities include implementation, analysis, and cross-team debugging to achieve timing, power, and manufacturability goals.

• Support block-level and/or top-level physical design: floorplanning, placement, clock tree synthesis, routing, and physical verification.
• Work with senior engineers to optimize timing, power, area, congestion, and routability.
• Participate in netlist handoff, constraints setup, synthesis/physical handoff, and signoff readiness.
• Run and analyze timing, power, congestion, and DRC/LVS reports to identify and resolve issues.
• Support static timing analysis (STA), timing closure, and ECO implementation.
• Debug setup/hold violations, clocking problems, congestion, IR drop, and other physical issues.
• Develop and maintain scripts and automation to improve flow efficiency.
• Support silicon bring-up and post-silicon debug activities as needed.

Requirements

Must-have technical skills and experience.

• Practical experience with physical design fundamentals: floorplanning, placement, CTS, routing, timing closure, and physical verification.
• Familiarity with industry physical design and signoff tools (examples: Cadence Innovus, Synopsys ICC2, PrimeTime, Fusion Compiler).
• Solid understanding of static timing analysis (STA), timing constraints, and setup/hold concepts.
• Experience reviewing and debugging timing, congestion, area, and power reports.
• Familiarity with DRC/LVS and signoff-quality physical verification checks.
• Experience scripting or automating flows using Tcl, Python, Perl, or similar languages.
• Knowledge of semiconductor design flows from RTL handoff through physical implementation and signoff.
• Strong digital design fundamentals and CMOS/VLSI concepts.

Nice-to-have:

• Experience with advanced-node physical design methodologies and low-power implementation.
• Exposure to FPGA, SoC, or high-performance product development.
• Familiarity with power planning, IR drop, signal integrity, electromigration analysis, or physical signoff flows.
• Experience working in Linux/Unix development environments.
• Strong problem-solving skills and ability to work collaboratively in cross-functional teams.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related engineering field is required; a Master’s is preferred. The role expects approximately 2+ years of industry experience in physical design or backend implementation. No specific certifications were listed.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.