Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

The Physical Design Engineer will implement advanced custom IP and SoC designs from RTL through GDSII and drive timing closure, power optimization, physical verification, and signoff for leading-edge FPGA and semiconductor products. This role is part of the Silicon Engineering and Physical Design organization and collaborates across architecture, RTL, DFT, synthesis, verification, and methodology teams.

Experience Level

Mid-level (typical experience: 3–7+ years). The posting requests at least 5+ years of semiconductor physical design experience.

Responsibilities

Primary responsibilities focus on physical implementation, verification, and cross-team collaboration to deliver manufacturing-ready designs.

• Implement full-chip and block-level physical design from RTL through GDSII and deliver manufacturing-ready design databases.
• Execute physical design flow: synthesis, floorplanning, power planning, placement & route, clock tree synthesis (CTS), timing closure, and physical optimization.
• Perform static timing analysis (STA); diagnose and resolve setup, hold, signal-integrity, and timing violations.
• Design and optimize clock distribution networks, power distribution networks, and multi-power-domain implementations.
• Perform physical verification and signoff activities (LEC, DRC, LVS, ERC, IR drop, electromigration, power integrity).
• Analyze implementation results, identify root causes, and drive corrective actions to improve product architectures.
• Optimize implementations for performance, power, area (PPA), manufacturability, and reliability.
• Integrate and support Design-for-Test (DFT) requirements through physical implementation and signoff.
• Collaborate with RTL, logic design, DFT, CAD, verification, architecture, and product engineering teams throughout the design cycle.
• Contribute to and automate physical design methodologies and flows; mentor junior engineers.

Requirements

Must-have skills and experience (education details moved to Education Requirements below):

• 5+ years of experience in semiconductor physical design, including implementing custom IP or SoC designs from RTL through GDSII.
• 5+ years with physical design flows: synthesis, floorplanning, place & route, CTS, and physical optimization.
• 3+ years performing static timing analysis (STA) and achieving timing closure on advanced designs.
• 3+ years with physical verification and signoff: DRC, LVS, ERC, LEC, IR drop, electromigration (EM), and power integrity analysis.
• Strong analytical and debugging skills for timing, congestion, and physical implementation challenges.
• Experience balancing power, performance, and area trade-offs across large-scale SoC designs.
• Ability to collaborate effectively across multidisciplinary engineering teams and to mentor junior engineers.

Nice-to-have:

• Experience with advanced process nodes (7nm, 5nm, 3nm or smaller) and high-performance CPU, FPGA, AI accelerator, or networking SoC designs.
• Scripting for flow automation (Tcl, Python, Perl, Shell).
• Knowledge of low-power implementation methodologies (UPF/CPF).

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline (required alongside the stated experience). Preferred: Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical discipline. The posting pairs the degree requirement with specified years of experience (e.g., Bachelor's + 5+ years).

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.