PHY/SERDES Lead
Volantis SemiconductorJob Title
PHY/SERDES Lead
Role Summary
Lead the design, delivery, and silicon bring-up of a semi-custom optical PHY layer. The role owns end-to-end link definition, PHY architecture, and delivery across specification, implementation, verification, and tapeout.
Experience Level
Senior — typically 7+ years of relevant experience in PHY/SERDES design and silicon delivery.
Responsibilities
Primary responsibilities include technical ownership of the PHY layer and coordination across design and system teams.
- Own and lead development of the semi-custom optical PHY layer from specification through tapeout and bring-up.
- Define end-to-end link architecture and trade-offs across SERDES classes (XSR/VSR/LR) and operating regimes.
- Drive PHY macro design, verification, and readiness for silicon tapeout.
- Plan and execute silicon bring-up, debug PHY link issues, and close silicon validation tasks.
- Integrate PHYs into system-level architecture and coordinate interfaces with SoC, chiplet, firmware, and verification teams.
- Specify and manage PHY customizations to meet product and system requirements.
- Provide technical leadership and mentorship to engineering teams and collaborate with cross-functional stakeholders.
Requirements
Strong demonstrable experience required; preferred skills listed separately.
Must-have:
- Multiple successful tapeouts of SERDES or PHY macros.
- Deep understanding of trade-offs and operating regimes for XSR, VSR, and LR class SERDES.
- Proven ownership of end-to-end link definition and PHY architecture.
- Experience with silicon PHY bring-up and debug.
- Experience integrating PHYs into system-level designs.
Nice-to-have:
- Hands-on experience with chiplet interfaces such as UCIe or BoW.
- Practical experience with optical interconnect PHY layers.
- Knowledge of re-driven and re-timed PHY interfaces.
- Experience customizing PHYs for specific product needs.
Education Requirements
Not specified.
About the Company
Company: Volantis Semiconductor
Semiconductor hardware startup developing wafer-scale heterogeneous packages that integrate silicon and compound semiconductor dies for high-TDP AI platforms. Focus areas include advanced packaging design and process development, interposer technologies, thermal/mechanical challenges, and system co-design.
