Ph.D. Intern - Analog, Mixed Signal & Circuit Design

Job Title

Ph.D. Intern — Analog, Mixed-Signal & Circuit Design

Role Summary

Join an analog and mixed-signal design team working on high-speed SerDes, silicon photonics drivers/receivers, ADC/DAC architectures, PLLs, clock distribution, LDOs and other precision analog IP for advanced CMOS nodes. The intern will be embedded in an active design team and take a design project through simulation, layout coordination, and silicon bring-up.

This role focuses on technical execution and learning: converting doctoral research into production-grade silicon while using industry-standard tools and collaborating with staff and layout engineers.

Experience Level

Entry-level (Internship). Intended for current Ph.D. candidates in electrical engineering or a closely related technical field.

Responsibilities

Work on transistor-level analog and mixed-signal circuit design across the full design flow and contribute to team engineering activities.

• Design, simulate, and verify analog/mixed-signal circuit blocks from architecture and schematic through simulation and silicon bring-up.
• Develop production-grade IP: high-speed SerDes blocks, photonics drivers/receivers, ADCs/DACs, PLLs, clock networks, LDOs, and precision analog circuits.
• Use Cadence tools and MATLAB (or Python) for circuit and system-level modeling.
• Collaborate with layout engineers and iterate designs based on post-layout simulation and silicon feedback.
• Participate in and present work at design reviews; document design decisions and tradeoffs.
• Complete a structured analog design curriculum alongside other Ph.D. interns.

Requirements

Core technical skills and practical experience required to perform the role. Preferred skills are listed separately.

Must-have:

• Hands-on transistor-level analog and mixed-signal circuit design experience (practical design and simulation, not just theoretical coursework).
• Experience designing or simulating blocks such as PLLs, SerDes building blocks, ADCs, DACs, LDOs, amplifiers, or high-speed I/O.
• Strong fundamentals in device physics, noise analysis, linearity, stability, and low-power techniques in advanced CMOS processes.
• Experience with Cadence (Virtuoso/Spectre) for simulation and verification.
• Ability to communicate design decisions clearly and present results to engineering teams.
• Willingness to work on production IP and follow a full chip design flow in a team environment.

Nice-to-have:

• Experience in FinFET process nodes (7nm, 5nm, 3nm or equivalent).
• Familiarity with high-speed serial link architectures, optical transceiver circuits, or die-to-die interconnects.
• Exposure to layout-aware design, parasitic extraction, or post-layout simulation.
• Behavioral modeling experience (Verilog-A) and MATLAB/Python for system-level modeling.

Education Requirements

Currently enrolled in a Ph.D. program in Electrical Engineering or a closely related field with a research focus in analog, mixed-signal, or RF circuit design. (Ph.D. enrollment is required for internship qualification.)

Reasonable accommodation requests during the selection process can be directed to Marvell HR Helpdesk at TAOps@marvell.com.

Note: Applicants may be subject to export control review; eligibility to access export-controlled information may be required.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.